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january 2004 i ? 2004 actel corporation see the actel website (www.actel.com) for the latest version of this datasheet. 40mx and 42mx fpga families features high capacity ? single-chip asic alternative 3,000 to 54,000 system gates up to 2.5 kbits configurable dual-port sram fast wide-decode circuitry up to 202 user-programmable i/o pins high performance 5.6 ns clock-to-out 250 mhz performance 5 ns dual-port sram access 100 mhz fifos 7.5 ns 35-bit address decode hirel features commercial, industrial, automotive, and military temperature plastic packages commercial, military temp erature, and mil-std-883 ceramic packages qml certification ceramic devices available to dscc smd ease of integration mixed-voltage operation (5.0v or 3.3v for core and i/os), with pci-compliant i/os up to 100% resource utilization and 100% pin locking deterministic, user -controllable timing unique in-system diagnostic and verification capability with silicon explorer ii low power consumption ieee standard 1149.1 (jtag) boundary scan testing product profile device a40mx02 a40mx04 A42MX09 a42mx16 a42mx24 a42mx36 capacity system gates sram bits 3,000 ? 6,000 ? 14,000 ? 24,000 ? 36,000 ? 54,000 2,560 logic modules sequential combinatorial decode ? 295 ? ? 547 ? 348 336 ? 624 608 ? 954 912 24 1,230 1,184 24 clock-to-out 9.5 ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns sram modules (64x4 or 32x8) ??? ? ?10 dedicated flip-flops ? ? 348 624 954 1,230 maximum flip-flops 147 273 516 928 1,410 1,822 clocks 112 2 26 user i/o (maximum) 57 69 104 140 176 202 pci ??? ?yesyes boundary scan test (bst) ??? ?yesyes packages (by pin count) plcc pqfp vqfp tqfp cqfp pbga 44, 68 100 80 ? ? ? 44, 68, 84 100 80 ? ? ? 84 100, 160 100 176 ? ? 84 100, 160, 208 100 176 ? ? 84 160, 208 ? 176 ? ? ? 208, 240 ? ? 208, 256 272 v6.0
40mx and 42mx fpga families ii v6.0 ordering information plastic device resources _ part number speed grade package type package lead count blank = commercial (0 to +70?c) i = industrial (?40 to +85?c) m = military (?55 to +125?c) b = mil-std-883 a = automotive (?40 to +125?c) application (temperature range) pl = plastic leaded chip carrier pq = plastic quad flat pack tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack bg = plastic ball grid array cq = ceramic quad flat pack blank = standard speed ?1 = approximately 15% faster than standard ?2 = approximately 25% faster than standard ?3 = approximately 35% faster than standard ?f = approximately 40% slower than standard a40mx02 = 3,000 system gates a40mx04 = 6,000 system gates A42MX09 = 14,000 system gates a42mx16 = 24,000 system gates a42mx24 = 36,000 system gates a42mx36 = 54,000 s y stem gates a42mx16 1 pq 100 es user i/os device plcc 44-pin plcc 68-pin plcc 84-pin pqfp 100-pin pqfp 160-pin pqfp 208-pin pqfp 240-pin vqfp 80-pin vqfp 100-pin tqfp 176-pin pbga 272-pin a40mx02 34 57 ? 57 ? ? ? 57 ? ? ? a40mx04 34 57 69 69 ? ? ? 69 ? ? ? A42MX09 ? ? 72 83 101 ? ? ? 83 104 ? a42mx16 ? ? 72 83 125 140 ? ? 83 140 ? a42mx24 ? ? 72 ? 125 176 ? ? ? 150 ? a42mx36?????176202???202 note: package definitions plcc = plastic leaded chip carrier, pqfp = pl astic quad flat pack, tqfp = thin quad flat pack, vqfp = very thin quad flat pack, pbga = plastic ball grid array
40mx and 42mx fpga families v6.0 iii ceramic device resources temperature grade offerings speed grade offerings contact your local actel represen tative for device availability. user i/os device cqfp 208-pin cqfp 256-pin a42mx36 176 202 note: package definitions cqfp = ceramic quad flat pack package a40mx02 a40mx04 A42MX09 a42mx16 a42mx24 a42mx36 plcc 44 c, i, m c, i, m plcc 68 c, i, a, m c, i, m plcc 84 c, i, a, m c, i, a, m c, i, m c, i, m pqfp 100 c, i, a, m c, i, a, m c, i, a, m c, i, m pqfp 160 c, i, a, m c, i, m c, i, a, m pqfp 208 c, i, a, m c, i, a, m c, i, a, m pqfp 240 c, i, a, m vqfp 80 c, i, a, m c, i, a, m vqfp 100 c, i, a, m c, i, a, m tqfp 176 c, i, a, m c, i, a, m c, i, a, m pbga 272 c, i, m cqfp 208 c, m, b cqfp 256 c, m, b note: c = commercial i = industrial a = automotive m = military b = mil-std-883 class b ? f std?1?2?3 c ????? i ???? a ? m ?? b ?? note: refer to the 40mx and 42mx automotive family fpgas datasheet for details on automotive-grade mx offerings.

v6.0 v table of contents 40mx and 42mx fpga families 40mx and 42mx fpga families general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 mx architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 other architectural features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 5.0v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 5v ttl electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 3.3v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 3.3v lvttl electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 mixed 5.0v/3.3v operating conditions (for 42mx devices only) . . . . . . . . . . . . . 1-18 mixed 5.0v/3.3v electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 output drive characteristics for 5. 0v pci signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19 output drive characteristics for 3.3v pci signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20 junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 timing models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 parameter measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 sequential module timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 sequential timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 decode module timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 sram timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 dual-port sram timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 predictable performance: tight delay distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 temperature and voltage derating fa ctors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 pci system timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 pci models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -35 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77 package pin assignments 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 68-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 84-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
vi v6.0 table of contents 40mx and 42mx fpga families 100-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 160-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 208-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 240-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 80-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 20 100-pin vqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 176-pin tqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 208-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 8 256-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 1 272-pin bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
40mx and 42mx fpga families v6.0 1-1 40mx and 42mx fpga families general description actel's 40mx and 42mx familie s offer a cost-effective design solution at 5v. the mx devices are single-chip solutions and provide high performance while shortening the system design and development cycle. mx devices can integrate and consolidate logic implemented in multiple pals, cplds, and fpgas. example applications includ e high-speed c ontrollers and address decoding, peripheral bus interfaces, dsp, and co- processor functions. the mx device architecture is based on actel?s patented antifuse technology implem ented in a 0.45m triple- metal cmos process. with capacities ranging from 3,000 to 54,000 system gates, the mx devices provide performance up to 250 mhz, are live on power-up and have one-fifth the standby power consumption of comparable fpgas. actel?s mx fpgas provide up to 202 user i/os and are available in a wide variety of packages and speed grades. actel?s a42mx24 and a42mx 36 devices also feature multiplex i/os, which suppor t mixed-voltage systems, enable programmable pci, deliver high-performance operation at both 5.0v an d 3.3v, and provide a low- power mode. the devices are fully compliant with the pci local bus specification (version 2.1). they deliver 200 mhz on-chip operation and 6.1 ns clock-to-output performance. the 42mx24 and 42mx36 devices include system-level features such as ieee stan dard 1149.1 (jtag) boundary scan testing and fast wide-d ecode modules. in addition, the a42mx36 device offers dual-port sram for implementing fast fifos, lifos, and temporary data storage. the storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and dsp. all mx devices are fully te sted over automotive and military temperature ranges. in addition, the largest member of the family, the a 42mx36, is available in both cq208 and cq256 ceramic packages screened to mil- std-883 levels. for easy prot otyping and conversion from plastic to ceramic, the cq208 and pq208 devices are pin- compatible. mx architectural overview the mx devices are composed of fine-grained building blocks that enable fast, efficient logic designs. all devices within these families are co mposed of logic modules, i/o modules, routing resources and clock networks, which are the building blocks for fast logic designs. in addition, the a42mx36 device contai ns embedded dual-port sram modules, which are optimized for high-speed datapath functions such as fifos, lifos and scratchpad memory. a42mx24 and a42mx36 also contain wide- decode modules. logic modules the 40mx logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources ( figure 1-1 ). the logic module can implem ent the four basic logic functions (nand, and, or and nor) in gates of two, three, or four inputs. the logic module can also implement a variety of d-latc hes, exclusivity functions, and-ors and or-ands. no dedicated hard-wired latches or flip-flops are required in the array; latches and flip- flops can be constructed from logic modules whenever required in the application. figure 1-1 ? 40mx logic module
40mx and 42mx fpga families 1-2 v6.0 the 42mx devices contain three types of logic modules: combinatorial (c-modules), sequential (s-modules) and decode (d-modules). figure 1-2 illustrates the combinatorial logic module . the s-module, shown in figure 1-3 , implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d-flip-flop or a tr ansparent latch. the s-module register can be bypassed so that it implements purely combinatorial logic. figure 1-2 42mx c-module implementation d00 d01 d10 d11 s0 s1 y a 0 b0 a1 b1 figure 1-3 42mx s-module implementation clr up to 7-input function plus d-type flip-flop with clear up to 4-input function plus latch with clear d0 d1 s y d q gate clr out up to 8-input function (same as c-module) d00 d01 d10 d11 s1 s0 y out up to 7-input function plus latch d00 d01 d10 d11 s1 s0 y ou t gate d q d00 d01 d10 d11 s1 s0 y d q out
40mx and 42mx fpga families v6.0 1-3 a42mx24 and a42mx36 devi ces contain d-modules, which are arranged around th e periphery of the device. d-modules contain wide-decode circuitry, providing a fast, wide-input and function similar to that found in cpld architectures ( figure 1-4 ). the d-module allows a42mx24 and a42mx36 devices to perform wide- decode functions at speeds comparable to cplds and pals. the output of the d-module has a programmable inverter for active high or low assertion. the d-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic. dual-port sram modules the a42mx36 device contains dual-port sram modules that have been optimized for synchronous or asynchronous applications. the sram modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. sram modules can be cascaded together to form memory spaces of user -definable width and depth. a block diagram of the a42m x36 dual-port sram block is shown in figure 1-5 . the a42mx36 sram module s are true dual-port structures containing independent read and write ports. each sram module contains six bits of read and write addressing (rdad[5:0] and wr ad[5:0], respectively) for 64x4-bit blocks. when config ured in byte mode, the highest order address bits (rdad5 and wrad5) are not used. the read and write ports of the sram block contain independent clocks (rclk and wclk) with programmable polarities offering active high or low implementation. the sram block contains eight data inputs (wd[7:0]), and eight outputs (rd[7:0]), which are connected to segmented vertical routing tracks. the a42mx36 dual-port sram bl ocks provide an optimal solution for high-speed buffered applications requiring fifo and lifo queues. the actgen macro builder within actel's designer software provides capability to quickly design memory functions with the sram blocks. unused sram blocks can be used to implement registers for other user logic within the design. figure 1-4 a42mx24 and a42mx36 d-module implementation 7 inputs hard-wire to i/o feedback to array programmable inverter figure 1-5 a42mx36 dual-port sram block sram module 32 x 8 or 64 x 4 (256 bits) read port logic write port logic rd [7: 0] routing tracks latches read logic [5:0] rdad[5:0] ren rclk latches wd [7: 0] latches wrad[5:0] write logic mod e blken wen wc lk [5:0] [7:0]
40mx and 42mx fpga families 1-4 v6.0 routing structure the mx architecture uses vert ical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are meta l interconnects that may be continuous or split into segments. varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. segments can be joined to gether at the ends using antifuses to increase their lengths up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between the rows of module s. any segment that spans more than one-third of the row length is considered a long horizontal segment. a typical channel is shown in figure 1-6 . within horizontal routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. non-dedicated tracks are used for signal nets. vertical routing another set of routing tracks run vertically through the module. there are three types of vertical tracks: input, output, and long. long tracks span the column length of the module, and can be divided into multiple segments. each segment in an input trac k is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted an d can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge ef fects occur. long vertical tracks contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 1-6 . antifuse structures an antifuse is a "normally open" structure. the use of antifuses to implement a programmable logic device results in highly testable stru ctures as well as efficient programming algorithms. th ere are no pre-existing connections; temporary connections can be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. for instance, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. clock networks the 40mx devices have one global clock distribution network (clk). a signal can be put on the clk network by being routed through the clkbuf buffer. in 42mx devices, there are two low-skew, high-fanout clock distribution networks, referred to as clka and clkb. each network has a clock module (clkmod) that can select the source of the clock signal from any of the following ( figure 1-7 on page 1-5 ): externally from the clka pad, using clkbuf buffer externally from the clkb pad, using clkbuf buffer internally from the clkinta input, using clkint buffer internally from the clkintb input, using clkint buffer the clock modules are loca ted in the top row of i/o modules. clock drivers and a dedicated horizontal clock track are located in each ho rizontal routing channel. clock input pads in both 40mx and 42mx devices can also be used as normal i/os, bypassing the clock networks. the a42mx36 device has four additional register control resources, called quadrant clock networks ( figure 1-8 on page 1-5 ). each quadrant clock provides a local, high- fanout resource to the contiguous logic modules within its quadrant of the device. quadrant clock signals can originate from specific i/o pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. figure 1-6 mx routing structure segmented horizontal routing logic modules antifuses vertical routing tracks
40mx and 42mx fpga families v6.0 1-5 figure 1-7 clock networks of 42mx devices note: *qclk1in, qclk2in, qclk3in, and qclk4in are internally-generated signals. figure 1-8 quadrant clock network of a42mx36 devices clkb clka from pads clock drivers clkmod clkinb clkina s0 s1 internal signal clko(17) clko(16) clko(15) clko(2) clko(1) clock tracks quad clock modul qclka qclkb *qclk1in s0 s1 qclk1 quad clock modul *qclk2in s0 s1 qclk2 quad clock modul qclkc qclkd *qclk3in s0 s1 qclk3 quad clock modul *qclk4in s0 s1 qclk4
40mx and 42mx fpga families 1-6 v6.0 multiplex i/o modules 42mx devices feature multip lex i/os and support 5.0v, 3.3v, and mixed 3.3v/5.0v operations. the multiplex i/o modules pr ovide the interface between the device pins and the logic array. figure 1-9 is a block diagram of the 42mx i/o module. a variety of user functions, determined by a library macro selection, can be implemented in the module. (refer to the antifuse macro library guide for more information.) all 42mx i/o modules contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation. all 42mx devices contain flex ible i/o structures, where each output pin has a dedicated output-enable control ( figure 1-9 ). the i/o module can be used to latch input or output data, or both, providing fast set-up time. in addition, the actel designer software tools can build a d- type flip-flop using a c-module combined with an i/o module to register input and output signals. refer to the antifuse macro library guide for more details. a42mx24 and a42mx36 devices also offer selectable pci output drives, enabling 100% compliance with version 2.1 of the pci specification. for low-power systems, all inputs and outputs are turned off to reduce current consumption to below 500 a. to achieve 5.0v or 3.3v pc i-compliant output drives on a42mx24 and a42mx36 devices, a chip-wide pci fuse is programmed via the device selection wizard in the designer software ( figure 1-10 ). when the pci fuse is not programmed, the output drive is standard. actel's designer software development tools provide a design library of i/o macro fu nctions that can implement all i/o configurations supported by the mx fpgas. other architectural features performance mx devices can operate with internal clock frequencies of 250 mhz, enabling fast ex ecution of complex logic functions. mx devices are live on power-up and do not require auxiliary configuration devices and thus are an optimal platform to integrate the functionality contained in multiple programmable logic devices. in addition, designs that previously would have required a gate array to meet performa nce can be integrated into an mx device with improvem ents in cost and time-to- market. using timing-drive n place-and-route (tdpr) tools, designers can achieve highly deterministic device performance. user security the actel fuselock provides robust security against design theft. special security fuses are hidden in the fabric of the device and pr event unauthoriz ed users from accessing the programming and/or probe interfaces. it is virtually impossible to identify or bypass these fuses without damaging the device, making actel antifuse fpgas immune to bo th invasive and noninvasive attacks. special security fuses in 40mx devices include the probe fuse and program fuse. the fo rmer disables the probing circuitry while the latter prohibits further programming of all fuses, including the probe fuse. in 42mx devices, there is the security fuse which, when programmed, both disables the probing circuitry and prohibits further programming of the device. look for this symbol to ensure your valuable ip is secure. for more information, refer to actel's implementation of security in actel antifuse fpgas application note. note: *can be configured as a latch or d flip-flop (using c-module) figure 1-9 42mx i/o module q d from array to array g/clk* g/clk* q d pad en figure 1-10 pci output structure of a42mx24 and a42mx36 devices signal pci enable pci fuse drive std output
40mx and 42mx fpga families v6.0 1-7 programming device programming is supp orted through the silicon sculptor series of programmer s. silicon sculptor ii is a compact, robust, single-site and multi-site device programmer for the pc. with standalone software, silicon sculptor ii is desi gned to allow concurrent programming of multiple units from the same pc. silicon sculptor ii programs devices independently to achieve the fastest program ming times possible. after being programmed, each fuse is verified to insure that it has been programmed correctl y. furthermore, at the end of programming, there are in tegrity tests that are run to ensure no extra fuses have been programmed. not only does it test fuses (both programmed and nonprogrammed), silicon sculpt or ii also allows self-test to verify its own hardware extensively. the procedure for programm ing an mx device using silicon sculptor ii is as follows: 1. load the .afm file 2. select the device to be programmed 3. begin programming when the design is ready to go to production, actel offers device volume-programming services either through distribution partners or via in-house programming from the factory. for more details on programming mx devices, please refer to the programming antifuse devices and the silicon sculptor ii user's guides. power supply mx devices are designed to operate in both 5.0v and 3.3v environments. in particular, 42mx devices can operate in mixed 5.0v/3.3v systems. table 1 describes the voltage support of mx devices. power-up/down in mixed-voltage mode when powering up 42mx in mixed voltage mode (v cca =5.0v and v cci = 3.3v), v cca must be greater than or equal to v cci throughout the power-up sequence. if v cci exceeds v cca during power up, ei ther the i/os' input protection junction on the i/os will be forward-biased or the i/os will be at logical high, and i cc rises to high levels. for power-down, any sequence with v cca and v cci can be implemented. low power mode 42mx devices have been designed with a low power mode. this feature, activate d with setting the special lp pin to high for a period longer than 800 ns, is particularly useful for batt ery-operated systems where battery life is a primary concer n. in this mode, the core of the device is turned off and the device consumes minimal power with low standby curr ent. in addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated. since the core of the device is turned off, the states of th e registers are lost. the device must be re-initialized when exiting low power mode. i/ os can be driven during lp mode, and clock pins should be driven high or low and should not float to avoid drawing current. to exit lp mode, the lp pin must be pulled low for over 200 s to allow for charge pumps to power up, and device in itialization will begin. figure 1-11 fuselock ? e u table 1 voltage support of mx devices device v cc v cca v cci maximum input tolerance nominal output voltage 40mx 5.0v ? ? 5.5v 5.0v 3.3v ? ? 3.6v 3.3v 42mx ? 5.0v 5.0v 5.5v 5.0v ? 3.3v 3.3v 3.6v 3.3v ? 5.0v 3.3v 5.5v 3.3v
40mx and 42mx fpga families 1-8 v6.0 power dissipation the general power consumption of mx devices is made up of static and dynamic power and can be expressed with the following equation: general power equation p = [i cc standby + i cc active] * v cci + i ol * v ol * n + i oh * (v cci ? v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, on design details, and on the system i/o. the power can be divided into two components: static and active. static power component the static power due to stan dby current is typically a small component of the overall power consumption. standby power is calculated for commercial, worst-case conditions. the static powe r dissipation by ttl loads depends on the number of outputs driving, and on the dc load current. for instan ce, a 32-bit bus sinking 4ma at 0.33v will generate 42mw with all outputs driving low, and 140mw with all outputs driving high. the actual dissipation will average so mewhere in between, as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the dynamic power dissipation. dynamic power consumption is frequency-dependent and is a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to pc board traces and load de vice inputs. an additional component of the active power dissipation is the totem pole current in the cmos tran sistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. the power dissipated by a cmos circuit can be expressed by the equation: power (w) = c eq * v cca 2 * f(1) where: c eq =equivalent capacitance expressed in picofarads (pf) v cca =power supply in volts (v) f =switching frequency in megahertz (mhz) equivalent capacitance equivalent capacitance is calculated by measuring i cc active at a specified freq uency and voltage for each circuit component of interest. measurements have been made over a range of freque ncies at a fixed value of v cc . equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq values for actel mx fpgas modules (c eqm )3.5 input buffers (c eqi )6.9 output buffers (c eqo )18.2 routed array clock buffer loads (c eqcr )1.4 to calculate the active pow er dissipated from the complete design, the switching frequency of each part of the logic must be known. the equation below shows a piece-wise linear summatio n over all components. power = v cca 2 * [(m x c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * ( c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 (2) where: m = number of logic modules switching at frequency f m n = number of input buffers switching at frequency f n p = number of output buffers switching at frequency f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock
40mx and 42mx fpga families v6.0 1-9 fixed capacitance values for mx fpgas (pf) test circuitry and si licon explorer ii probe mx devices contain probing circuitry that provides built- in access to every node in a design, via the use of silicon explorer ii. silicon explorer ii is an integrated hardware and software solution that, in conjunction with the designer software, allow users to examine any of the internal nets of the device while it is operating in a prototyping or a production system. the user can probe into an mx device without changing the placement and routing of the design and without using any additional resources. silicon explorer ii's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle and providing a true representation of the device under actual functional situations. silicon explorer ii samples data at 100 mhz (asynchronous) or 66 mhz (syn chronous). silicon explorer ii attaches to a pc's standa rd com port, turning the pc into a fully functional 18-channel logic analyzer. silicon explorer ii allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. silicon explorer ii is used to control the mode, dclk, sdi and sdo pins in mx devices to select the desired nets for debugging. the user simply assigns the selected internal nets in the silicon explorer ii software to the pra/prb output pins for observation. probing functionality is activated when the mode pin is held high. figure 1-12 illustrates the interconnection between silicon explorer ii and 40mx devices, while figure 1-13 on page 1-10 illustrates the interconnection between silicon explorer ii and 42mx devices to allow for probing capabilit ies, the security fuses must not be programmed. (refer to ?user security? section on page 6 for the security fuses of 40mx and 42mx devices). table 2 on page 1-10 summarizes the possible device config urations for probing. pra and prb pins are dual -purpose pins. when the "reserve probe pin" is checked in the designer software, pra and prb pins are reserved as dedicated outputs for probing. if pra and prb pins are required as user i/os to ac hieve successful layout and "reserve probe pin" is ch ecked, the layout tool will override the option and pl ace user i/os on pra and prb pins. c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output load capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz device type r 1 routed_clk1 r 2 routed_clk2 a40mx02 41.4 n/a a40mx04 68.6 n/a A42MX09 118 118 a42mx16 165 165 a42mx24 185 185 a42mx36 220 220 figure 1-12 silicon explorer ii setup with 40mx 40mx silicon explorer ii pra prb sdo dclk sdi mode serial connection to windows pc 16 logic analyzer channels
40mx and 42mx fpga families 1-10 v6.0 design consideration it is recommended to use a series 70 ? termination resistor on every probe connector (sdi, sdo, mode, dclk, pra and prb). the 70 ? series termination is used to prevent data transmission corruption during probing and reading back the checksum. ieee standard 1149.1 boundary scan test (bst) circuitry 42mx24 and 42mx36 devices are compatible with ieee standard 1149.1 (informally known as joint testing action group standard or jtag), which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. the basic mx boundary-scan logic circuit is composed of the tap (test access port), tap controller, test data registers and instruction register ( figure 1-14 on page 1-11 ). this circuit supports all mandatory ieee 1149.1 instructions (extest, sample/ preload and bypass) and some optional instructions. table 3 on page 1-11 describes the ports that control jtag testing, while table 4 on page 1-11 describes the test instructions supported by these mx devices. each test section is accessed through the tap, which has four associated pins: tck (t est clock input), tdi and tdo (test data input and out put), and tms (test mode selector). the tap controller is a four -bit state machine. the '1's and '0's represent the values that must be present at tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architec ture. on power-up, the tap controller enters the test-log ic-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. 42mx24 and 42mx36 devices s upport three types of test data registers: bypass, device identification, and boundary scan. the bypass regi ster is selected when no other register needs to be accessed in a device. this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lowest significant byte (lsb), id number, part number and version). the boundary-scan register observ es and controls the state of each i/o pin. figure 1-13 silicon explorer ii setup with 42mx table 2 device configuration options for probe capability security fuse(s) programmed mode pra, prb 1 sdi, sdo, dclk 1 no low user i/os 2 user i/os 2 no high probe circuit outputs probe circuit inputs yes ? probe circuit secured probe circuit secured notes: 1. avoid using sdi, sdo, dclk, pra and prb pins as input or bidi rectional ports. since these pins are active during probing, inp ut signals will not pass through thes e pins and may cause contention. 2. if no user signal is assigned to these pins, they will behave as unused i/os in this mode. see the ?pin descriptions? section on page 77 for information on unused i/o pins. 42mx silicon explorer ii pra prb sdo dclk sdi mode serial connection to windows pc 16 logic analyzer channels
40mx and 42mx fpga families v6.0 1-11 each i/o cell has three boundary -scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which st arts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic tile and the input, output and control ports of an i/o buffer to capt ure and load data into the register to control or observ e the logic state of each i/o. figure 1-14 42mx ieee 1149.1 boundary scan circuitry table 3 test access port descriptions port description tms (test mode select) serial input for the test logic control bits. data is capt ured on the rising edge of the test logic clock (tck). tck (test clock input) dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge of the clock, and serially to shift the output data on th e falling edge of the clock. the maximum clock frequency for tck is 20 mhz. tdi (test data input) serial input for instruction and test data. da ta is captured on the rising edge of the test logic clock. tdo (test data output) serial output for test instruction and data from the test logic. tdo is set to an inactive drive state (high impedance) when data scanning is not in progress. table 4 supported bst public instructions instruction ir code (ir2.ir0) instruction type description extest 000 mandatory allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. sample/preload 001 mandatory allows a snapshot of the signals at the device pins to be captured and examined during operation high z 101 optional tristates all i/os to allow external signals to drive pins. please refer to the ieee standa rd 1149.1 specification. clamp 110 optional allows state of signals driven from component pins to be determined from the boundary-scan register. please refer to the ieee standard 1149.1 sp ecification for details. bypass 111 mandatory enables the bypass regi ster between the tdi and tdo pins. the test data passes through the selected device to adjacent devices in the test chain. boundary scan register instruction decode control logic tap controller instruction register bypass register tms tck tdi output mux tdo jtag jtag
40mx and 42mx fpga families 1-12 v6.0 jtag mode activation the jtag test logic circuit is activated in the designer software by selecting tools -> device selection. this brings up the device selection dialog box as shown in figure 1-15 . the jtag test logic circuit can be enabled by clicking the "reserve jtag pins" check box. table 5 explains the pins' behavior in either mode. trst pin and tap controller reset an active reset (trst) pin is not supported; however, mx devices contain power-on circuitry that resets the boundary scan circuitry upon power-up. also, the tms pin is equipped with an internal pull-up resistor. this allows the tap controller to remain in or return to the test-logic-reset state when th ere is no input or when a logical 1 is on the tms pin. to reset the controller, tms must be high for at least five tck cycles. boundary scan description language (bsdl) file conforming to the ieee stan dard 1149.1 requires that the operation of the various jtag components be documented. the bsdl file pr ovides the standard format to describe the jtag components that can be used by automatic test equipment software. the file includes the instructions that are supported, instruction bit pattern, and the boundary-scan chain order. for an in-depth discussion on bsdl files, please refer to actel bsdl files format description application note. actel bsdl files are grouped into two categories - generic and device-specific. the generic files assign all user i/os as inouts. device-spe cific files assign user i/os as inputs, outputs or inouts. generic files for mx devices are available on actel's website at http://www.actel.com/tec hdocs/models/bsdl.html . figure 1-15 device selection wizard table 5 boundary scan pin configuration and functionality reserve jtag checked unchecked tck bst input; must be terminated to logi cal high or low to avoid floating user i/o tdi, tms bst input; may float or be tied to high user i/o tdo bst output; may float or be connected to tdi of another device user i/o
40mx and 42mx fpga families v6.0 1-13 development tool support the mx family of fpgas is fu lly supported by both actel's libero? integrated design environment and designer fpga development software. actel libero ide is a design management environment th at streamlines the design flow. libero ide provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment. libero ide includes synplify? for acte l from synplicity?, viewdraw for actel from mentor graphics, modelsim? hdl simulator from mentor graphics?, waveformer lite? from synapticad?, and designer software from actel. refer to the libero ide flow (located on actel?s website) diagram for more information. actel's designer software is a place-and-route tool and provides a comprehensive suit e of backend support tools for fpga development. the designer software includes timing-driven place-and-r oute, and a world-class integrated static timing an alyzer and constraints editor. with the designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. additionally, the back- annotation flow is compat ible with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, actel?s integrated verification and logic analysis tool. anot her tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as me ntor graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as mentor gr aphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. related documents application notes actel bsdl files format description www.actel.com/documen ts/bsdlformat_an.pdf programming antifuse devices http://www.actel.com/documents/ antifuseprogram_an.pdf actel's implementation of security in actel antifuse fpgas www.actel.com/documents/antifuse_security_an.pdf user?s guides and manuals antifuse macro library guide www.actel.com/documents/libguide_ug.pdf silicon sculptor ii www.actel.com/techdocs/manuals/default.asp#programmers miscellaneous libero ide flow diagram www.actel.com/products/tools/libero/flow.html
40mx and 42mx fpga families 1-14 v6.0 5.0v operating conditions table 6 absolute maximum rati ngs for 40mx devices* symbol parameter limits units v cc dc supply voltage ?0.5 to +7.0 v v i input voltage ?0.5 to v cc +0.5 v v o output voltage ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder "absolute maximum ratings" may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 7 absolute maximum rati ngs for 42mx devices* symbol parameter limits units v cci dc supply voltage for i/os ?0.5 to +7.0 v v cca dc supply voltage for array ?0.5 to +7.0 v v i input voltage ?0.5 to v cci +0.5 v v o output voltage ?0.5 to v cci +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder "absolute maximum ratings" may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 8 recommended operating conditions parameter commercial i ndustrial military units temperature range* 0 to +70 -40 to +85 ?55 to +125 c v cc (40mx) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 v v cca (42mx) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 v v cci (42mx) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 v note: *ambient te mperature (t a ) is used for commercial and industrial grades; case temperature (t c ) is used for military grades.
40mx and 42mx fpga families v6.0 1-15 5v ttl electrical specifications table 9 5v ttl electrical specifications symbol parameter commercial commercial -f industrial military units min. max. min. max. min. max. min. max. v oh 1 i oh = -10ma 2.4 2.4 v i oh = -4ma 3.7 3.7 v v ol 1 i ol = 10ma 0.5 0.5 v i ol = 6ma 0.4 0.4 v v il -0.3 0.8 -0.3 0.8 -0.3 0.8 -0.3 0.8 v v ih (40mx) 2.0 v cc +0.3 2.0 v cc +0.3 2.0 v cc +0.3 2.0 v cc +0.3 v v ih (42mx) 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 v i il v in = 0.5v -10 -10 -10 -10 a i ih v in = 2.7v -10 -10 -10 -10 a input transition time, t r and t f 500 500 500 500 ns c io i/o capacitance 10101010pf standby current, i cc 2 a40mx02, a40mx04 3 251025ma A42MX09 5 25 25 25 ma a42mx16 6 25 25 25 ma a42mx24, a42mx36 20 25 25 25 ma low-power mode standby current 42mx devices only 0.5 i cc - 5.0 i cc - 5.0 i cc - 5.0 ma i io , i/o source sink current can be derived from the ibis model (http://www.actel.com/techdocs/models/ibis.html) notes: 1. only one output tested at a time. v cc /v cci = min. 2. all outputs unloaded. all inputs = v cc /v cci or gnd.
40mx and 42mx fpga families 1-16 v6.0 3.3v operating conditions table 10 absolute maximum rati ngs for 40mx devices* symbol parameter limits units v cc dc supply voltage ?0.5 to +7.0 v v i input voltage ?0.5 to v cc +0.5 v v o output voltage ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder "absolute maximum ratings" may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 11 absolute maximum rati ngs for 42mx devices* symbol parameter limits units v cci dc supply voltage for i/os ?0.5 to +7.0 v v cca dc supply voltage for array ?0.5 to +7.0 v v i input voltage ?0.5 to v cci +0.5 v v o output voltage ?0.5 to v cci +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder "absolute maximum ratings" may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 12 recommended operating conditions parameter commercial i ndustrial military units temperature range* 0 to +70 ?40 to +85 ?55 to +125 c v cc (40mx) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v v cca (42mx) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v v cci (42mx) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v note: *ambient te mperature (t a ) is used for commercial and industrial grades; case temperature (t c ) is used for military grades.
40mx and 42mx fpga families v6.0 1-17 3.3v lvttl electrical specifications table 13 3.3v lvttl electrical specifications symbol parameter commercial commercial -f industrial military units min. max. min. max. min. max. min. max. v oh 1 i oh = ?4ma 2.15 2.15 2.4 2.4 v v ol 1 i ol = 6ma 0.4 0.4 0.48 0.48 v v il ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v v ih (40mx) 2.0 v cc +0.3 2.0 v cc +0.3 2.0 v cc +0.3 2.0 v cc +0.3 v v ih (42mx) 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 v i il ?10 ?10 ?10 ?10 a i ih ?10 ?10 ?10 ?10 a input transition time, t r and t f 500 500 500 500 ns c io i/o capacitance 10 10 10 10 pf standby current, i cc 2 a40mx02, a40mx04 3251025ma A42MX09 5 25 25 25 ma a42mx16 6 25 25 25 ma a42mx24, a42mx36 15 25 25 25 ma low-power mode standby current 42mx devices only 0.5 i cc - 5.0 i cc - 5.0 i cc - 5.0 ma i io , i/o source sink current can be derived from the ibis model ( http://www.actel.com/tec hdocs/models/ibis.html) notes: 1. only one output tested at a time. v cc /v cci = min. 2. all outputs unloaded. all inputs = v cc /v cci or gnd.
40mx and 42mx fpga families 1-18 v6.0 mixed 5.0v/3.3v operating conditions (for 42mx devices only) mixed 5.0v/3.3v electrical specifications table 14 absolute maximum ratings* symbol parameter limits units v cci dc supply voltage for i/os ?0.5 to +7.0 v v cca dc supply voltage for array ?0.5 to +7.0 v v i input voltage ?0.5 to v cci +0.5 v v o output voltage ?0.5 to v cci +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder "absolute maximum ratings" may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 15 recommended operating conditions parameter commercial i ndustrial military units temperature range* 0 to +70 -40 to +85 ?55 to +125 c v cca 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 v v cci 3.14 to 3.47 3.0 to 3.6 3.0 to 3.6 v note: *ambient te mperature (t a ) is used for commercial and industrial grades; case temperature (t c ) is used for military grades. table 16 mixed 5.0v/3.3v electrical specifications symbol parameter commercial commercial '-f 'industrial military units min. max. min. max. min. max. min. max. v oh 1 i oh = ?10ma 2.4 2.4 v i oh = ?4ma 3.7 3.7 v v ol 1 i ol = 10ma 0.5 0.5 v i ol = 6ma 0.4 0.4 v v il ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v v ih 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 2.0 v cci +0.3 v i l v in = 0.5v ?10 ?10 ?10 ?10 a i h v in = 2.7v ?10 ?10 ?10 ?10 a input transition time, t r and t f 500 500 500 500 ns c io i/o capacitance 10 10 10 10 pf standby current, i cc 2 A42MX09 5 25 25 25 ma a42mx16 6 25 25 25 ma a42mx24, a42mx36 20 25 25 25 ma low-power mode standby current 0.5 i cc - 5.0 i cc - 5.0 i cc - 5.0 ma i io i/o source sink current can be derived from the ibis model ( http://www.actel.com/techdocs/models/ibis.html) notes: 1. only one output tested at a time. v cci = min. 2. all outputs unloaded. all inputs = v cci or gnd.
40mx and 42mx fpga families v6.0 1-19 output drive characteristics for 5.0v pci signaling mx pci device i/o drivers were designed spec ifically for high-perfo rmance pci systems. figure 1-16 on page 1-21 shows the typical output drive characteristics of the mx device s. mx output drivers are co mpliant with the pci local bus specification. table 17 dc specification (5.0v pci signaling) 1 pci mx symbol parameter condition min. max. min. max. units v cci supply voltage for i/os 4.75 5.25 4.75 5.25 2 v v ih input high voltage 2.0 v cc + 0.5 2.0 v cci + 0.3 v v il input low voltage ?0.5 0.8 ?0.3 0.8 v i ih input high leakage current v in = 2.7v 70 ? 10 a i il input low leakage current v in =0.5v ?70 ? ?10 a v oh output high voltage i out = ?2 ma i out = ?6 ma 2.4 3.84 v v ol output low voltage i out = 3 ma, 6 ma 0.55 ? 0.33 v c in input pin capacitance 10 ? 10 pf c clk clk pin capacitance 5 12 ? 10 pf l pin pin inductance 20 ? < 8 nh 3 nh notes: 1. pci local bus specification, version 2.1, section 4.2.1.1. 2. maximum rating for v cci ?0.5v to 7.0v. 3. dependent upon the chosen package. pci recommends qfp a nd bga packaging to reduce pin inductance and capacitance. table 18 ac specifications (5 .0v pci signaling)* pci mx symbol parameter condition min. max. min. max. units i cl low clamp current ?5 < v in ?1 ?25 + (v in +1) /0.015 ?60 ?10 ma slew (r) output rise slew rate 0.4v to 2.4v load 1 5 1.8 2.8 v/ns slew (f) output fall slew rate 2.4v to 0.4v load 1 5 2.8 4.3 v/ns note: *pci local bus specification, version 2.1, section 4.2.1.2.
40mx and 42mx fpga families 1-20 v6.0 output drive characteristics for 3.3v pci signaling table 19 dc specification (3.3v pci signaling) 1 pci mx symbol parameter condition min. max. min. max. units v cci supply voltage for i/os 3.0 3.6 3.0 3.6 v v ih input high voltage 0.5 v cc + 0.5 0.5 v cci + 0.3 v v il input low voltage ?0.5 0.8 ?0.3 0.8 v i ih input high leakage current v in = 2.7v 70 10 a i il input leakage current ?70 ?10 a v oh output high voltage i out = ?2 ma 0.9 3.3 v v ol output low voltage i out = 3 ma, 6 ma 0.1 0.1 v cci v c in input pin capacitance 10 10 pf c clk clk pin capacitance 5 12 10 pf l pin pin inductance 20 < 8 nh 3 nh notes: 1. pci local bus specification, version 2.1, section 4.2.2.1. 2. maximum rating for v cci ?0.5v to 7.0v. 3. dependent upon the chosen package. pci recommends qfp a nd bga packaging to reduce pin inductance and capacitance. table 20 ac specifications for (3.3v pci signaling)* pci mx symbol parameter condition min. max. min. max. units i cl low clamp current ?5 < v in ?1 ?25 + (v in +1) /0.015 ?60 ?10 ma slew (r) output rise slew rate 0.2v to 0.6v load 1 4 1.8 2.8 v/ns slew (f) output fall slew rate 0.6v to 0.2v load 1 4 2.8 4.0 v/ns note: *pci local bus specification, version 2.1, section 4.2.2.2.
40mx and 42mx fpga families v6.0 1-21 figure 1-16 typical output drive characterist ics (based upon measured data) 01 2 3 4 5 6 mx pci i ol mx pci i oh pci i ol maximum pci i ol minimum pci i oh minimum pci i oh maximum voltage out (v) ?0.20 ?0.15 ?0.10 ?0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current (a)
40mx and 42mx fpga families 1-22 v6.0 junction temperature (t j ) the temperature variable in the designer software refers to the junction temper ature, not the ambient temperature. this is an impor tant distinction because the heat generated from dynamic power consumption is usually hotter than th e ambient temperature. eq 1-1 , shown below, can be used to calculate junction temperature. eq 1-1 junction temperature = ? t + t a (1) where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ja * p(2) p = power ja = junction to ambient of package. ja numbers are located in the package ther mal characteristics table below. package thermal characteristics the device junction-to-case thermal characteristic is jc , and the junction-to-ambien t air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. the maximum junction temperature is 150 c. maximum power dissipation for commercial- and industrial-grade devices is a function of ja . a sample calculation of the absolute maximum power dissipation allowed for a tqfp 176-pin package at commercial temperature an d still air is as follow: the maximum power dissipat ion for military-grade devi ces is a function of jc . a sample calculation of the absolute maximum power dissipation allowed for cqfp 208-pin packag e at military temperature and still air is as follows: table 21 package thermal characteristics plastic packages pin count jc ja units still air 1.0 m/s 200 ft/min. 2.5 m/s 500 ft/min. plastic quad flat pack 100 12.0 27.8 23.4 21.2 c/w plastic quad flat pack 160 10.0 26.2 22.8 21.1 c/w plastic quad flat pack 208 8.0 26.1 22.5 20.8 c/w plastic quad flat pack 240 8.5 25.6 22.3 20.8 c/w plastic leaded chip carri er 44 16.0 20.0 24.5 22.0 c/w plastic leaded chip carri er 68 13.0 25.0 21.0 19.4 c/w plastic leaded chip carri er 84 12.0 22.5 18.9 17.6 c/w thin plastic quad flat pack 176 11.0 24.7 19.9 18.0 c/w very thin plastic quad flat pack 80 12.0 38.2 31.9 29.4 c/w very thin plastic quad flat pack 100 10.0 35.3 29.4 27.1 c/w plastic ball grid array 272 3.0 18.3 14.9 13.9 c/w ceramic packages ceramic quad flat pack 208 2.0 22.0 19.8 18.0 c/w ceramic quad flat pack 256 2.0 20.0 16.5 15.0 c/w maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -- 150 c70 c ? 28 c/w ---------------------------------- - 2.86w = = = maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? jc ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -- 150 c 125 c ? 6.3 c/w ------------------------------------- - 3.97w = = =
40mx and 42mx fpga families v6.0 1-23 timing models note: * values are shown for 40mx ??3? speed device s at 5.0v worst-case commercial conditions. figure 1-17 40mx timing model* notes: *values are shown for A42MX09 ??3? at 5. 0v worst-case comm ercial conditions. ? input module predicted routing delay. figure 1-18 42mx timing model* output delay input delay logic module internal delays t dlh=3.32 ns t enhz=7.92 ns t rd1=1.28 ns t rd2=1.80 ns t rd4=2.33 ns t rd8=4.93 ns i/o module t pd=1.24 ns t co=1.24 ns t ird1=2.09 ns t ird4=3.64 ns t ird8=5.73 ns t inyl=0.62 ns t ird2=2.59 ns i/o module f max=180 mhz t ckh=4.55 ns fo=128 array clock predicted routing delays array clocks combin - at o r ia l logic include dq fo = 32 output delays internal delays input delays i/o module dq ? combinatorial logic module sequential logic module i/o module i/o module dq predicted ro uti ng delays g g t rd1=0.7 ns t rd2=1.9 ns t rd4=1.4 ns t rd8=2.3 ns t outh=0.00 ns t outsu=0.3 ns t glh=2.6 ns t dlh=2.5 ns t dlh=2.5 ns t enhz=4.9 ns t rd1=0.70 ns t lco=5.2 ns (light loads, pad-to-pad) t co=1.3 ns t sud=0.3 ns t hd=0.00 ns t pd=1.2 ns t ird1=2.0 ns t inyl=0.8 ns t inh=0.0 ns t insu=0.3 ns t ingl=1.3 ns f max=296 mhz t ckh=2.70 ns
40mx and 42mx fpga families 1-24 v6.0 notes: * values are shown for a42mx36 ??3? at 5.0v worst-case commercial conditions. ** load-dependent figure 1-19 42mx timing model (logic functions using quadrant clocks) note: *values are shown for a42mx36 ??3 at 5. 0v worst-case commercial conditions. figure 1-20 42mx timing model (sram functions) array clocks combin - at o r ia l logic include dq fo = 32 output delays internal delays input delays i/o module dq ? combinatorial logic module sequential logic module i/o module i/o module dq predicted ro uti ng delays g g t rd1=0.7 ns t rd2=1.9 ns t rd4=1.4 ns t rd8=2.3 ns t outh=0.00 ns t outsu=0.3 ns t glh=2.6 ns t dlh=2.5 ns t dlh=2.5 ns t enhz=4.9 ns t rd1=0.70 ns t lco=5.2 ns (light loads, pad-to-pad) t co=1.3 ns t sud=0.3 ns t hd=0.00 ns t pd=1.2 ns t ird1=2.0 ns t inyl=0.8 ns t inh=0.0 ns t insu=0.3 ns t ingl=1.3 ns f max=296 mhz t ckh=2.70 ns t inpy=1.0ns input delays i/o module dq array clocks g i/o module dq g wd [7:0] wrad [5:0] blken wen wclk rd [7:0] r dad [ 5:0] ren rclk predicte d routing delays t ghl=2.9ns t lsu=0.5ns t lh=0.0ns t dlh=2.6ns t adsu=1.6ns t adh=0.0ns t rensu=0.6ns t rco=3.4ns t adsu=1.6ns t adh=0.0ns t wensu=2.7ns t bens=2.8ns t rd1=0.9ns f max =167 mhz t ird1=2.0ns t insu=0.5ns t inh=0.0ns t ingo=1.4ns
40mx and 42mx fpga families v6.0 1-25 parameter measurement figure 1-21 output buffer delays figure 1-22 ac test loads to ac test loads (shown below) pad d e tribuff in 50% pa d 1.5v 50% 1.5v e 50% pa d 1.5v 50% 10% e 50% pa d gnd 1.5v 50% 90% t enzl t enlz t enzh t enhz t dlh t dhl v ol v oh v cci v ol v oh 35 pf load 1 (used to measure propagation delay) to the output under test to the output under test load 2 (used to measure rising/falling edges) v cci gnd 35 pf ? r to v cci for t plz/ t pzl r to gnd for t phz/ t pzh r=1k figure 1-23 input buffer delays pa d y in buf pa d 3v 0v 1.5v y gnd 50% 1.5v 50% t inyl t inyh v cci figure 1-24 module delays s a b y s, a or b y 50% t plh y 50% 50% 50% 50% 50% t phl phl t plh
40mx and 42mx fpga families 1-26 v6.0 sequential module timing characteristics note: *d represents all da ta functions involving a, b, a nd s for multiplexed flip-flops. figure 1-25 flip-flops and latches t wclka t wasyn t hd t su en a t sud t rs t a t wclki t co t hena d* g, clk e q pre, clr (positive edge-triggered) d e clk clr pre y
40mx and 42mx fpga families v6.0 1-27 sequential timing characteristics figure 1-26 input buffer latches figure 1-27 output buffer latches g pa d pa d clk data g clk t inh t insu t su ex t t hext ibdl data d g t outsu t outh pad obdlhs d g
40mx and 42mx fpga families 1-28 v6.0 decode module timing sram timing characteristics dual-port sram timing waveforms figure 1-28 decode module timing figure 1-29 sram timing characteristics note: identical timing for falling edge clock. figure 1-30 42mx sram write operation a?g, h y t plh 50% t phl y a b c d e f g h wrad [5:0] blken wen wc lk rdad [5:0] lew ren rc lk rd [7:0] wd [ 7:0] write port read port ram array 3 2x8 or 64x4 (2 56 bits) wclk wd [7: 0] wrad[5:0] wen blken valid valid t rckhl t rckhl t wensu t bensu t wenh t benh t adsu t adh
40mx and 42mx fpga families v6.0 1-29 note: identical timing for falling edge clock. figure 1-31 42mx sram synchronou s read operation figure 1-32 42mx sram asynchronous read operat ion?type 1 (read ad dress controlled) figure 1-33 42mx sram asynchronous read operat ion?type 2 (write address controlled) rclk ren rdad[5:0] rd[7:0] old data valid t rckhl t ckhl t renh t rco t adh t doh t adsu new data t rensu rdad[5:0] rd[7:0] data 1 t rdadv t doh addr2 addr1 data 2 t rpd wen wd[7:0] wclk rd[7:0] old data valid t wenh t rpd t wensu new data t doh t adsu wrad[5:0] blken t adh
40mx and 42mx fpga families 1-30 v6.0 predictable performance: tight delay distributions propagation delay between logic modules depends on the resistive and capacitive lo ading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay in creases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer routing tracks. the mx fpgas deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. actel?s patented antifuse offers a very low resistive/ capacitive interconnect. the antifuses, fabricated in 0.45 m lithography, offer nominal levels of 100 ? resistance and 7.0ff capacitance per antifuse. mx fanout distribution is also tight due to the low number of antifuses required for each interconnect path. the proprietary architectu re limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses. timing characteristics device timing characteristics fall into three categories: family-dependent, device-dependent, and design- dependent. the input and output buffer characteristics are common to all mx device s. internal routing delays are device-dependent; actual delays are not determined until after place-and-route of the user's design is complete. delay values may th en be determined by using the designer software utility or by performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most timing critical paths. critical nets are determined by net property assignment in actel's designer software prior to placement and ro uting. up to 6% of the nets in a design may be designated as critical. long tracks some nets in the design use long tracks, which are special routing resources th at span multiple rows, columns, or modules. long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6 percent of nets in a fully utilized device require long tracks. long tracks add appr oximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (fo=8) routing delays in th e data sheet specifications section, shown in table 28 on page 1-36 . timing derating mx devices are manufactured with a cmos process. therefore, device perfor mance varies according to temperature, voltage, and process changes. minimum timing parameters reflect maximum operating voltage, minimum operating temp erature and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature and worst-case processing.
40mx and 42mx fpga families v6.0 1-31 temperature and voltage derating factors table 22 42mx temperature and voltage derating factors (normalized to t j = 25c, v cca = 5.0v) 42mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 4.50 0.93 0.95 1.05 1. 09 1.25 1.29 1.41 4.75 0.88 0.90 1.00 1. 03 1.18 1.22 1.34 5.00 0.85 0.87 0.96 1. 00 1.15 1.18 1.29 5.25 0.84 0.86 0.95 0. 97 1.12 1.14 1.28 5.50 0.83 0.85 0.94 0. 96 1.10 1.13 1.26 note: this derating factor applies to all routing and pr opagation delays. figure 1-34 42mx junction temperature and voltage derating curves (normalized to t j = 25c, v cca = 5.0v) 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 4.50 4.75 5.00 5.25 5.50 voltage (v) derating factor ?55?c ?40?c 0?c 25?c 70?c 85?c 125?c
40mx and 42mx fpga families 1-32 v6.0 table 23 40mx temperature and voltage derating factors (normalized to t j = 25c, v cc = 5.0v) 40mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 4.50 0.89 0.93 1.02 1.09 1.25 1.31 1.45 4.75 0.84 0.88 0.97 1.03 1.18 1.24 1.37 5.00 0.82 0.85 0.94 1.00 1.15 1.20 1.33 5.25 0.80 0.82 0.91 0.97 1.12 1.16 1.29 5.50 0.79 0.82 0.90 0.96 1.10 1.15 1.28 note: this derating factor applies to all routing and pr opagation delays. figure 1-35 40mx junction temperature and voltage derating curves (normalized to t j = 25c, v cc = 5.0v) factor 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 4.50 4.75 5.00 5.25 5.50 voltage (v) derating ?55?c ?40?c 0?c 25?c 70?c 85?c 125?c
40mx and 42mx fpga families v6.0 1-33 table 24 42mx temperature and voltage derating factors (normalized to t j = 25c, v cca = 3.3v) 42mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 3.00 0.97 1.00 1.10 1.15 1.32 1.36 1.45 3.30 0.84 0.87 0.96 1.00 1.15 1.18 1.26 3.60 0.81 0.84 0.92 0.96 1.10 1.13 1.21 note: this derating factor applies to all routing and pr opagation delays. figure 1-36 42mx junction temperature and voltage derating curves (normalized to t j = 25c, v cca = 3.3v) (v) 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 voltage (v) derating factor 3.00 3.30 3.60 55?c 40?c 0?c 25?c 70?c 85?c 125?c
40mx and 42mx fpga families 1-34 v6.0 table 25 40mx temperature and voltage derating factors (normalized to t j = 25c, v cc = 3.3v) 40mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 3.00 1.08 1.12 1.21 1.26 1.50 1.64 2.00 3.30 0.86 0.89 0.96 1.00 1.19 1.30 1.59 3.60 0.83 0.85 0.92 0.96 1.14 1.25 1.53 note: this derating factor applies to all routing and pr opagation delays. figure 1-37 40mx junction temperature and voltage derating curves (normalized to t j = 25c, v cc = 3.3v) 3.00 3.30 3.60 voltage (v) derating factor 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 55?c 40?c 0?c 25?c 70?c 85?c 125?c
40mx and 42mx fpga families v6.0 1-35 pci system timing specification table 26 and table 27 list the critical pci timing parameters and the corresponding timing parameters for the mx pci-compliant devices. pci models actel provides synthesizable vhdl and verilog-hdl models for a pci target in terface, a pci target and target+dma master interface. contact your actel sales representative for more details. table 26 clock specification for 33 mhz pci symbol parameter pci a42mx24 a42mx36 units min. max. min. max. min. max. t cyc clk cycle time 30 ? 4.0 ? 4.0 ? ns t high clk high time 11 ? 1.9 ? 1.9 ? ns t low clk low time 11 ?1.9?1.9? ns table 27 timing parameters for 33 mhz pci pci a42mx24 a42mx36 symbolparameter min.max.min.max.min.max.units t val clk to signal valid?bused signals 2 11 2.0 9.0 2.0 9.0 ns t val(ptp) clk to signal valid?point-to-point 2 2 12 2.0 9.0 2.0 9.0 ns t on float to active 2 ? 2.0 4.0 2.0 4.0 ns t off active to float ? 28 ? 8.3 1 ?8.3 1 ns t su input set-up time to clk?bused signals 7 ? 1.5 ? 1.5 ? ns t su(ptp) input set-up time to clk?point-to-point 10, 12 2 ?1.5?1.5? ns t h input hold to clk 0 ? 0 ? 0 ? ns notes: 1. t off is system dependent. mx pci device s have 7.4 ns turn-off time, reflecti on is typically an additional 10 ns. 2. req# and gnt# are point-to-poi nt signals and have different output valid dela y and input setup times than do bussed signals. gnt# has a setup of 10; rew# has a setup of 12.
40mx and 42mx fpga families 1-36 v6.0 timing characteristics table 28 a40mx02 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. min. max. min. max. min. max. min. max. logic module propagation delays t pd1 single module 1.2 1.4 1.6 1.9 2.7 ns t pd2 dual-module macros 2.7 3.1 3.5 4.1 5.7 ns t co sequential clock-to-q 1.2 1.4 1.6 1.9 2.7 ns t go latch g-to-q 1.2 1.4 1.6 1.9 2.7 ns t rs flip-flop (latch) rese t-to-q 1.2 1.4 1.6 1.9 2.7 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.3 1.5 1.7 2.0 2.8 ns t rd2 fo=2 routing delay 1.8 2.1 2.4 2.8 3.9 ns t rd3 fo=3 routing delay 2.3 2.7 3.0 3.6 5.0 ns t rd4 fo=4 routing delay 2.9 3.3 3.7 4.4 6.1 ns t rd8 fo=8 routing delay 4.9 5.7 6.5 7.6 10.6 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 3.1 3.5 4.0 4.7 6.6 ns t hd 3 flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 3.1 3.5 4.0 4.7 6.6 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.3 3.8 4.3 5.0 7.0 ns t wasyn flip-flop (latch) asynchronous pulse width 3.3 3.8 4.3 5.0 7.0 ns t a flip-flop clock input period 4.8 5.6 6.3 7.5 10.4 ns f max flip-flop (latch) clock frequency (fo = 128) 181 168 154 134 80 mhz input module propagation delays t inyh pad-to-y high 0.7 0.8 0.9 1.1 1.5 ns t inyl pad-to-y low 0.6 0.7 0.8 1.0 1.3 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35pf loading.
40mx and 42mx fpga families v6.0 1-37 input module predicted routing delays 1 t ird1 fo=1 routing delay 2.1 2.4 2.2 3.2 4.5 ns t ird2 fo=2 routing delay 2.6 3.0 3.4 4.0 5.6 ns t ird3 fo=3 routing delay 3.1 3.6 4.1 4.8 6.7 ns t ird4 fo=4 routing delay 3.6 4.2 4.8 5.6 7.8 ns t ird8 fo=8 routing delay 5.7 6.6 7.5 8.8 12.4 ns global clock network t ckh input low to high fo = 16 fo = 128 4.6 4.6 5.3 5.3 6.0 6.0 7.0 7.0 9.8 9.8 ns t ckl input high to low fo = 16 fo = 128 4.8 4.8 5.6 5.6 6.3 6.3 7.4 7.4 10.4 10.4 ns t pwh minimum pulse width high fo = 16 fo = 128 2.2 2.4 2.6 2.7 2.9 3.1 3.4 3.6 4.8 5.1 ns t pwl minimum pulse width low fo = 16 fo = 128 2.2 2.4 2.6 2.7 2.9 3.01 3.4 3.6 4.8 5.1 ns t cksw maximum skew fo = 16 fo = 128 0.4 0.5 0.5 0.6 0.5 0.7 0.6 0.8 0.8 1.2 ns t p minimum period fo = 16 fo = 128 4.7 4.8 5.4 5.6 6.1 6.3 7.2 7.5 10.0 10.4 ns f max maximum frequency fo = 16 fo = 128 188 181 175 168 160 154 139 134 83 80 mhz table 28 a40mx02 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. min. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35pf loading.
40mx and 42mx fpga families 1-38 v6.0 ttl output module timing 4 t dlh data-to-pad high 3.3 3.8 4.3 5.1 7.2 ns t dhl data-to-pad low 4.0 4.6 5.2 6.1 8.6 ns t enzh enable pad z to high 3.7 4.3 4.9 5.8 8.0 ns t enzl enable pad z to low 4.7 5.4 6.1 7.2 10.1 ns t enhz enable pad high to z 7.9 9.1 10.4 12.2 17.1 ns t enlz enable pad low to z 5.9 6.8 7.7 9.0 12.6 ns d tlh delta low to high 0.02 0.02 0.03 0.03 0.04 ns/pf d thl delta high to low 0.03 0.03 0.03 0.04 0.06 ns/pf cmos output module timing 4 t dlh data-to-pad high 3.9 4.5 5.1 6.05 8.5 ns t dhl data-to-pad low 3.4 3.9 4.4 5.2 7.3 ns t enzh enable pad z to high 3.4 3.9 4.4 5.2 7.3 ns t enzl enable pad z to low 4.9 5.6 6.4 7.5 10.5 ns t enhz enable pad high to z 7.9 9.1 10.4 12.2 17.0 ns t enlz enable pad low to z 5.9 6.8 7.7 9.0 12.6 ns d tlh delta low to high 0.03 0.04 0.04 0.05 0.07 ns/pf d thl delta high to low 0.02 0.02 0.03 0.03 0.04 ns/pf table 28 a40mx02 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. min. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35pf loading.
40mx and 42mx fpga families v6.0 1-39 table 29 a40mx02 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units logic module propagation delays t pd1 single module 1.7 2.0 2.3 2.7 3.7 ns t pd2 dual-module macros 3.7 4.3 4.9 5.7 8.0 ns t co sequential clock-to-q 1.7 2.0 2.3 2.7 3.7 ns t go latch g-to-q 1.7 2.0 2.3 2.7 3.7 ns t rs flip-flop (latch) reset-to-q 1.7 2.0 2.3 2.7 3.7 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 2.0 2.2 2.5 3.0 4.2 ns t rd2 fo=2 routing delay 2.7 3.1 3.5 4.1 5.7 ns t rd3 fo=3 routing delay 3.4 3.9 4.4 5.2 7.3 ns t rd4 fo=4 routing delay 4.2 4.8 5.4 6.3 8.9 ns t rd8 fo=8 routing delay 7.1 8.2 9.2 10.9 15.2 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 4.3 4.9 5.6 6.6 9.2 ns t hd 3 flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 4.3 4.9 5.6 6.6 9.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.6 5.3 6.0 7.0 9.8 ns t wasyn flip-flop (latch) asynchronous pulse width 4.6 5.3 6.0 7.0 9.8 ns t a flip-flop clock input period 6.8 7.8 8.9 10.4 14.6 ns f max flip-flop (latch) clock frequency (fo = 128) 109 101 92 80 48 mhz input module propagation delays t inyh pad-to-y high 1.0 1.1 1.3 1.5 2.1 ns t inyl pad-to-y low 0.9 1.0 1.1 1.3 1.9 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families 1-40 v6.0 input module predicted routing delays 1 t ird1 fo=1 routing delay 2.9 3.4 3.8 4.5 6.3 ns t ird2 fo=2 routing delay 3.6 4.2 4.8 5.6 7.8 ns t ird3 fo=3 routing delay 4.4 5.0 5.7 6.7 9.4 ns t ird4 fo=4 routing delay 5.1 5.9 6.7 7.8 11.0 ns t ird8 fo=8 routing delay 8.0 9.26 10.5 12.6 17.3 ns global clock network t ckh input low to high fo = 16 fo = 128 6.4 6.4 7.4 7.4 8.3 8.3 9.8 9.8 13.7 13.7 ns t ckl input high to low fo = 16 fo = 128 6.7 6.7 7.8 7.8 8.8 8.8 10.4 10.4 14.5 14.5 ns t pwh minimum pulse width high fo = 16 fo = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns t pwl minimum pulse width low fo = 16 fo = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns t cksw maximum skew fo = 16 fo = 128 0.6 0.8 0.6 0.9 0.7 1.0 0.8 1.2 1.2 1.6 ns t p minimum period fo = 16 fo = 128 6.5 6.8 7.5 7.8 8.5 8.9 10.1 10.4 14.1 14.6 ns f max maximum frequency fo = 16 fo = 128 113 109 105 101 96 92 83 80 50 48 mhz ttl output module timing 4 t dlh data-to-pad high 4.7 5.4 6.1 7.2 10.0 ns t dhl data-to-pad low 5.6 6.4 7.3 8.6 12.0 ns t enzh enable pad z to high 5.2 6.0 6.8 8.1 11.3 ns t enzl enable pad z to low 6.6 7.6 8.6 10.1 14.1 ns t enhz enable pad high to z 11.1 12.8 14.5 17.1 23.9 ns t enlz enable pad low to z 8.2 9.5 10.7 12.6 17.7 ns d tlh delta low to high 0.03 0.03 0.04 0.04 0.06 ns/pf d thl delta high to low 0.04 0.04 0.05 0.06 0.08 ns/pf table 29 a40mx02 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-41 cmos output module timing 4 t dlh data-to-pad high 5.5 6.4 7.2 8.5 11.9 ns t dhl data-to-pad low 4.8 5.5 6.2 7.3 10.2 ns t enzh enable pad z to high 4.7 5.5 6.2 7.3 10.2 ns t enzl enable pad z to low 6.8 7.9 8.9 10.5 14.7 ns t enhz enable pad high to z 11.1 12.8 14.5 17.1 23.9 ns t enlz enable pad low to z 8.2 9.5 10.7 12.6 17.7 ns d tlh delta low to high 0.05 0.05 0.06 0.07 0.10 ns/pf d thl delta high to low 0.03 0.03 0.04 0.04 0.06 ns/pf table 29 a40mx02 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families 1-42 v6.0 table 30 a40mx04 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module propagation delays t pd1 single module 1.2 1.4 1.6 1.9 2.7 ns t pd2 dual-module macros 2.3 3.1 3.5 4.1 5.7 ns t co sequential clock-to-q 1.2 1.4 1.6 1.9 2.7 ns t go latch g-to-q 1.2 1.4 1.6 1.9 2.7 ns t rs flip-flop (latch) reset-to-q 1.2 1.4 1.6 1.9 2.7 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.2 1.6 1.8 2.1 3.0 ns t rd2 fo=2 routing delay 1.9 2.2 2.5 2.9 4.1 ns t rd3 fo=3 routing delay 2.4 2.8 3.2 3.7 5.2 ns t rd4 fo=4 routing delay 2.9 3.4 3.9 4.5 6.3 ns t rd8 fo=8 routing delay 5.0 5.8 6.6 7.8 10.9 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 3.1 3.5 4.0 4.7 6.6 ns t hd 3 flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 3.1 3.5 4.0 4.7 6.6 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.3 3.8 4.3 5.0 7.0 ns t wasyn flip-flop (latch) asynchronous pulse width 3.3 3.8 4.3 5.0 7.0 ns t a flip-flop clock input period 4.8 5.6 6.3 7.5 10.4 ns f max flip-flop (latch) clock frequency (fo = 128) 181 167 154 134 80 mhz input module propagation delays t inyh pad-to-y high 0.7 0.8 0.9 1.1 1.5 ns t inyl pad-to-y low 0.6 0.7 0.8 1.0 1.3 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns . use the timer utility from the designer software to check the ho ld time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-43 input module predicted routing delays 1 t ird1 fo=1 routing delay 2.1 2.4 2.2 3.2 4.5 ns t ird2 fo=2 routing delay 2.6 3.0 3.4 4.0 5.6 ns t ird3 fo=3 routing delay 3.1 3.6 4.1 4.8 6.7 ns t ird4 fo=4 routing delay 3.6 4.2 4.8 5.6 7.8 ns t ird8 fo=8 routing delay 5.7 6.6 7.5 8.8 12.4 ns global clock network t ckh input low to high fo = 16 fo = 128 4.6 4.6 5.3 5.3 6.0 6.0 7.0 7.0 9.8 9.8 ns t ckl input high to low fo = 16 fo = 128 4.8 4.8 5.6 5.6 6.3 6.3 7.4 7.4 10.4 10.4 ns t pwh minimum pulse width high fo = 16 fo = 128 2.2 2.4 2.6 2.7 2.9 3.1 3.4 3.6 4.8 5.1 ns t pwl minimum pulse width low fo = 16 fo = 128 2.2 2.4 2.6 2.7 2.9 3.01 3.4 3.6 4.8 5.1 ns t cksw maximum skew fo = 16 fo = 128 0.4 0.5 0.5 0.6 0.5 0.7 0.6 0.8 0.8 1.2 ns t p minimum period fo = 16 fo = 128 4.7 4.8 5.4 5.6 6.1 6.3 7.2 7.5 10.0 10.4 ns f max maximum frequency fo = 16 fo = 128 188 181 175 168 160 154 139 134 83 80 mhz ttl output module timing 4 t dlh data-to-pad high 3.3 3.8 4.3 5.1 7.2 ns t dhl data-to-pad low 4.0 4.6 5.2 6.1 8.6 ns t enzh enable pad z to high 3.7 4.3 4.9 5.8 8.0 ns t enzl enable pad z to low 4.7 5.4 6.1 7.2 10.1 ns t enhz enable pad high to z 7.9 9.1 10.4 12.2 17.1 ns t enlz enable pad low to z 5.9 6.8 7.7 9.0 12.6 ns d tlh delta low to high 0.02 0.02 0.03 0.03 0.04 ns/pf d thl delta high to low 0.03 0.03 0.03 0.04 0.06 ns/pf table 30 a40mx04 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns . use the timer utility from the designer software to check the ho ld time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families 1-44 v6.0 cmos output module timing 1 t dlh data-to-pad high 3.9 4.5 5.1 6.05 8.5 ns t dhl data-to-pad low 3.4 3.9 4.4 5.2 7.3 ns t enzh enable pad z to high 3.4 3.9 4.4 5.2 7.3 ns t enzl enable pad z to low 4.9 5.6 6.4 7.5 10.5 ns t enhz enable pad high to z 7.9 9.1 10.4 12.2 17.0 ns t enlz enable pad low to z 5.9 6.8 7.7 9.0 12.6 ns d tlh delta low to high 0.03 0.04 0.04 0.05 0.07 ns/pf d thl delta high to low 0.02 0.02 0.03 0.03 0.04 ns/pf table 30 a40mx04 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cc = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns . use the timer utility from the designer software to check the ho ld time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-45 table 31 a40mx04 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module propagation delays t pd1 single module 1.7 2.0 2.3 2.7 3.7 ns t pd2 dual-module macros 3.7 4.3 4.9 5.7 8.0 ns t co sequential clock-to-q 1.7 2.0 2.3 2.7 3.7 ns t go latch g-to-q 1.7 2.0 2.3 2.7 3.7 ns t rs flip-flop (latch) reset-to-q 1.7 2.0 2.3 2.7 3.7 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.9 2.2 2.5 3.0 4.2 ns t rd2 fo=2 routing delay 2.7 3.1 3.5 4.1 5.7 ns t rd3 fo=3 routing delay 3.4 3.9 4.4 5.2 7.3 ns t rd4 fo=4 routing delay 4.1 4.8 5.4 6.3 8.9 ns t rd8 fo=8 routing delay 7.1 8.1 9.2 10.9 15.2 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 4.3 5.0 5.6 6.6 9.2 ns t hd 3 flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 4.3 5.0 5.6 6.6 9.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.6 5.3 5.6 7.0 9.8 ns t wasyn flip-flop (latch) asynchronous pulse width 4.6 5.3 5.6 7.0 9.8 ns t a flip-flop clock input period 6.8 7.8 8.9 10.4 14.6 ns f max flip-flop (latch) clock frequency (fo = 128) 109 101 92 80 48 mhz input module propagation delays t inyh pad-to-y high 1.0 1.1 1.3 1.5 2.1 ns t inyl pad-to-y low 0.9 1.0 1.1 1.3 1.9 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families 1-46 v6.0 input module predicted routing delays 1 t ird1 fo=1 routing delay 2.9 3.3 3.8 4.5 6.3 ns t ird2 fo=2 routing delay 3.6 4.2 4.8 5.6 7.8 ns t ird3 fo=3 routing delay 4.4 5.0 5.7 6.7 9.4 ns t ird4 fo=4 routing delay 5.1 5.9 6.7 7.8 11.0 ns t ird8 fo=8 routing delay 8.0 9.3 10.5 12.4 17.2 ns global clock network t ckh input low to high fo = 16 fo = 128 6.4 6.4 7.4 7.4 8.4 8.4 9.9 9.9 13.8 13.8 ns t ckl input high to low fo = 16 fo = 128 6.8 6.8 7.8 7.8 8.9 8.9 10.4 10.4 14.6 14.6 ns t pwh minimum pulse width high fo = 16 fo = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns t pwl minimum pulse width low fo = 16 fo = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns t cksw maximum skew fo = 16 fo = 128 0.6 0.8 0.6 0.9 0.7 1.0 0.8 1.2 1.2 1.6 ns t p minimum period fo = 16 fo = 128 6.5 6.8 7.5 7.8 8.5 8.9 10.1 10.4 14.1 14.6 ns f max maximum frequency fo = 16 fo = 128 113 109 105 101 96 92 83 80 50 48 mhz ttl output module timing 4 t dlh data-to-pad high 4.7 5.4 6.1 7.2 10.0 ns t dhl data-to-pad low 5.6 6.4 7.3 8.6 12.0 ns t enzh enable pad z to high 5.2 6.0 6.9 8.1 11.3 ns t enzl enable pad z to low 6.6 7.6 8.6 10.1 14.1 ns t enhz enable pad high to z 11.1 12.8 14.5 17.1 23.9 ns t enlz enable pad low to z 8.2 9.5 10.7 12.6 17.7 ns d tlh delta low to high 0.03 0.03 0.04 0.04 0.06 ns/pf d thl delta high to low 0.04 0.04 0.05 0.06 0.08 ns/pf table 31 a40mx04 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-47 cmos output module timing 4 t dlh data-to-pad high 5.5 6.4 7.2 8.5 11.9 ns t dhl data-to-pad low 4.8 5.5 6.2 7.3 10.2 ns t enzh enable pad z to high 4.7 5.5 6.2 7.3 10.2 ns t enzl enable pad z to low 6.8 7.9 8.9 10.5 14.7 ns t enhz enable pad high to z 11.1 12.8 14.5 17.1 23.9 ns t enlz enable pad low to z 8.2 9.5 10.7 12.6 17.7 ns d tlh delta low to high 0.05 0.05 0.06 0.07 0.10 ns/pf d thl delta high to low 0.03 0.03 0.04 0.04 0.06 ns/pf table 31 a40mx04 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cc = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the timer tool from the desi gner software to check the hold time for this macro. 4. delays based on 35 pf loading.
40mx and 42mx fpga families 1-48 v6.0 table 32 A42MX09 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module propagation delays 1 t pd1 single module 1.2 1.3 1.5 1.8 2.5 ns t co sequential clock-to-q 1.3 1.4 1.6 1.9 2.7 ns t go latch g-to-q 1.2 1.4 1.6 1.8 2.6 ns t rs flip-flop (latch) reset-to-q 1.2 1.6 1.8 2.1 2.9 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 0.7 0.8 0.9 1.0 1.4 ns t rd2 fo=2 routing delay 0.9 1.0 1.2 1.4 1.9 ns t rd3 fo=3 routing delay 1.2 1.3 1.5 1.7 2.4 ns t rd4 fo=4 routing delay 1.4 1.5 1.7 2.0 2.9 ns t rd8 fo=8 routing delay 2.3 2.6 2.9 3.4 4.8 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input set-up 0.3 0.4 0.4 0.5 0.7 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.4 0.5 0.5 0.6 0.8 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.4 3.8 4.3 5.0 7.0 ns t wasyn flip-flop (latch) asynchronous pulse width 4.5 4.9 5.6 6.6 9.2 ns t a flip-flop clock input period 3.5 3.8 4.3 5.1 7.1 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.3 0.3 0.4 0.4 0.6 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.3 0.3 0.4 0.4 0.6 ns f max flip-flop (latch) clock frequency 268 244 224 195 117 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-49 input module propagation delays t inyh pad-to-y high 1.0 1.2 1.3 1.6 2.2 ns t inyl pad-to-y low 0.8 0.9 1.0 1.2 1.7 ns t ingh g to y high 1.3 1.4 1.6 1.9 2.7 ns t ingl g to y low 1.3 1.4 1.6 1.9 2.7 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 2.0 2.2 2.5 3.0 4.2 ns t ird2 fo=2 routing delay 2.3 2.5 2.9 3.4 4.7 ns t ird3 fo=3 routing delay 2.5 2.8 3.2 3.7 5.2 ns t ird4 fo=4 routing delay 2.8 3.1 3.5 4.1 5.7 ns t ird8 fo=8 routing delay 3.7 4.1 4.7 5.5 7.7 ns global clock network t ckh input low to high fo = 32 fo = 256 2.4 2.7 2.7 3.0 3.0 3.4 3.6 4.0 5.0 5.5 ns ns t ckl input high to low fo = 32 fo = 256 3.5 3.9 3.9 4.3 4.4 4.9 5.2 5.7 7.3 8.0 ns ns t pwh minimum pulse width high fo = 32 fo = 256 1.2 1.3 1.4 1.5 1.5 1.7 1.8 2.0 2.5 2.7 ns ns t pwl minimum pulse width low fo = 32 fo = 256 1.2 1.3 1.4 1.5 1.5 1.7 1.8 2.0 2.5 2.7 ns ns t cksw maximum skew fo = 32 fo = 256 0.3 0.3 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 ns ns t suext input latch external set-up fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 256 2.3 2.2 2.6 2.4 3.0 3.3 3.5 3.9 4.9 5.5 ns ns t p minimum period fo = 32 fo = 256 3.4 3.7 3.7 4.1 4.0 4.5 4.7 5.2 7.8 8.6 ns ns f max maximum frequency fo = 32 fo = 256 296 268 269 244 247 224 215 195 129 117 mhz mhz table 32 A42MX09 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-50 v6.0 ttl output module timing 5 t dlh data-to-pad high 2.5 2.7 3.1 3.6 5.1 ns t dhl data-to-pad low 2.9 3.2 3.6 4.3 6.0 ns t enzh enable pad z to high 2.6 2.9 3.3 3.9 5.5 ns t enzl enable pad z to low 2.9 3.2 3.7 4.3 6.1 ns t enhz enable pad high to z 4.9 5.4 6.2 7.3 10.2 ns t enlz enable pad low to z 5.3 5.9 6.7 7.9 11.1 ns t glh g-to-pad high 2.6 2.9 3.3 3.8 5.3 ns t ghl g-to-pad low 2.6 2.9 3.3 3.8 5.3 ns t lsu i/o latch set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 5.2 5.8 6.6 7.7 10.8 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 7.4 8.2 9.3 10.9 15.3 ns d tlh capacity loading, low to hi gh 0.03 0.03 0.03 0.04 0.06 ns/pf d thl capacity loading, high to low 0.04 0.04 0.04 0.05 0.07 ns/pf table 32 A42MX09 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-51 cmos output module timing 5 t dlh data-to-pad high 2.4 2.7 3.1 3.6 5.1 ns t dhl data-to-pad low 2.9 3.2 3.6 4.3 6.0 ns t enzh enable pad z to high 2.7 2.9 3.3 3.9 5.5 ns t enzl enable pad z to low 2.9 3.2 3.7 4.3 6.1 ns t enhz enable pad high to z 4.9 5.4 6.2 7.3 10.2 ns t enlz enable pad low to z 5.3 5.9 6.7 7.9 11.1 ns t glh g-to-pad high 4.2 4.6 5.2 6.1 8.6 ns t ghl g-to-pad low 4.2 4.6 5.2 6.1 8.6 ns t lsu i/o latch set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 5.2 5.8 6.6 7.7 10.8 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 7.4 8.2 9.3 10.9 15.3 ns d tlh capacity loading, low to hi gh 0.03 0.03 0.03 0.04 0.06 ns/pf d thl capacity loading, high to low 0.04 0.04 0.04 0.05 0.07 ns/pf table 32 A42MX09 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-52 v6.0 table 33 A42MX09 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module propagation delays 1 t pd1 single module 1.6 1.8 2.1 2.5 3.5 ns t co sequential clock-to-q 1.8 2.0 2.3 2.7 3.8 ns t go latch g-to-q 1.7 1.9 2.1 2.5 3.5 ns t rs flip-flop (latch) reset-to-q 2.0 2.2 2.5 2.9 4.1 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.0 1.1 1.2 1.4 2.0 ns t rd2 fo=2 routing delay 1.3 1.4 1.6 1.9 2.7 ns t rd3 fo=3 routing delay 1.6 1.8 2.0 2.4 3.3 ns t rd4 fo=4 routing delay 1.9 2.1 2.4 2.9 4.0 ns t rd8 fo=8 routing delay 3.2 3.6 4.1 4.8 6.7 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input set-up 0.5 0.5 0.6 0.7 0.9 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.6 0.6 0.7 0.8 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.7 5.3 6.0 7.0 9.8 ns t wasyn flip-flop (latch) asynchronous pulse width 6.2 6.9 7.8 9.2 12.9 ns t a flip-flop clock input period 5.0 5.6 6.2 7.1 9.9 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.3 0.3 0.3 0.4 0.6 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.3 0.3 0.3 0.4 0.6 ns f max flip-flop (latch) clock frequency 161 146 135 117 70 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-53 input module propagation delays t inyh pad-to-y high 1.5 1.6 1.8 2.17 3.0 ns t inyl pad-to-y low 1.2 1.3 1.4 1.7 2.4 ns t ingh g to y high 1.8 2.0 2.3 2.7 3.7 ns t ingl g to y low 1.8 2.0 2.3 2.7 3.7 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 2.8 3.2 3.6 4.2 5.9 ns t ird2 fo=2 routing delay 3.2 3.5 4.0 4.7 6.6 ns t ird3 fo=3 routing delay 3.5 3.9 4.4 5.2 7.3 ns t ird4 fo=4 routing delay 3.9 4.3 4.9 5.7 8.0 ns t ird8 fo=8 routing delay 5.2 5.8 6.6 7.7 10.8 ns global clock network t ckh input low to high fo = 32 fo = 256 4.1 4.5 4.5 5.0 5.1 5.6 6.0 6.7 8.4 9.3 ns ns t ckl input high to low fo = 32 fo = 256 5.0 5.4 5.5 6.0 6.2 6.8 7.3 8.0 10.2 11.2 ns ns t pwh minimum pulse width high fo = 32 fo = 256 1.7 1.9 1.9 2.1 2.1 2.3 2.5 2.7 3.5 3.8 ns ns t pwl minimum pulse width low fo = 32 fo = 256 1.7 1.9 1.9 2.1 2.1 2.3 2.5 2.7 3.5 3.8 ns ns t cksw maximum skew fo = 32 fo = 256 0.4 0.4 0.5 0.5 0.5 0.5 0.6 0.6 0.9 0.9 ns ns t suext input latch external set-up fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 256 3.3 3.7 3.7 4.1 4.2 4.6 4.9 5.5 6.9 7.6 ns ns t p minimum period fo = 32 fo = 256 5.6 6.1 6.2 6.8 6.7 7.4 7.8 8.5 12.9 14.2 ns ns f max maximum frequency fo = 32 fo = 256 177 161 161 146 148 135 129 117 77 70 mhz mhz table 33 A42MX09 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-54 v6.0 ttl output module timing 5 t dlh data-to-pad high 3.4 3.8 4.3 5.1 7.1 ns t dhl data-to-pad low 4.0 4.5 5.1 6.1 8.3 ns t enzh enable pad z to high 3.7 4.1 4.6 5.5 7.6 ns t enzl enable pad z to low 4.1 4.5 5.1 6.1 8.5 ns t enhz enable pad high to z 6.9 7.6 8.6 10.2 14.2 ns t enlz enable pad low to z 7.5 8.3 9.4 11.1 15.5 ns t glh g-to-pad high 5.8 6.5 7.3 8.6 12.0 ns t ghl g-to-pad low 5.8 6.5 7.3 8.6 12.0 ns t lsu i/o latch set-up 0.7 0.8 0.9 1.0 1.4 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to- out (pad-to-pad), 64 clock loading 8.7 9.7 10.9 12.9 18.0 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 12.2 13.5 15.4 18.1 25.3 ns d tlh capacity loading, low to high 0.00 0.00 0.00 0.10 0.01 ns/pf d thl capacity loading, high to low 0.09 0.10 0.10 0.10 0.10 ns/pf table 33 A42MX09 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-55 cmos output module timing 5 t dlh data-to-pad high 3.4 3.8 5.5 6.4 9.0 ns t dhl data-to-pad low 4.1 4.5 4.2 5.0 7.0 ns t enzh enable pad z to high 3.7 4.1 4.6 5.5 7.6 ns t enzl enable pad z to low 4.1 4.5 5.1 6.1 8.5 ns t enhz enable pad high to z 6.9 7.6 8.6 10.2 14.2 ns t enlz enable pad low to z 7.5 8.3 9.4 11.1 15.5 ns t glh g-to-pad high 5.8 6.5 7.3 8.6 12.0 ns t ghl g-to-pad low 5.8 6.5 7.3 8.6 12.0 ns t lsu i/o latch set-up 0.7 0.8 0.9 1.0 1.4 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 8.7 9.7 10.9 12.9 18.0 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 12.2 13.5 15.4 18.1 25.3 ns d tlh capacity loading, low to hi gh 0.04 0.04 0.05 0.06 0.08 ns/pf d thl capacity loading, high to low 0.05 0.05 0.06 0.07 0.10 ns/pf table 33 A42MX09 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-56 v6.0 table 34 a42mx16 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module propagation delays 1 t pd1 single module 1.4 1.5 1.7 2.0 2.8 ns t co sequential clock-to-q 1.4 1.6 1.8 2.1 3.0 ns t go latch g-to-q 1.4 1.5 1.7 2.0 2.8 ns t rs flip-flop (latch) reset-to-q 1.6 1.7 2.0 2.3 3.3 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 0.8 0.9 1.0 1.2 1.6 ns t rd2 fo=2 routing delay 1.0 1.2 1.3 1.5 2.1 ns t rd3 fo=3 routing delay 1.3 1.4 1.6 1.9 2.7 ns t rd4 fo=4 routing delay 1.6 1.7 2.0 2.3 3.2 ns t rd8 fo=8 routing delay 2.6 2.9 3.2 3.8 5.3 ns logic module sequential timing 3,4 t sud flip-flop (latch) data input set-up 0.3 0.4 0.4 0.5 0.7 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.7 0.8 0.9 1.0 1.4 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.4 3.8 4.3 5.0 7.1 ns t wasyn flip-flop (latch) asynchronous pulse width 4.5 5.0 5.6 6.6 9.2 ns t a flip-flop clock input period 6.8 7.6 8.6 10.1 14.1 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.5 0.5 0.6 0.7 1.0 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.5 0.5 0.6 0.7 1.0 ns f max flip-flop (latch) clock frequency 215 195 179 156 94 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-57 input module propagation delays t inyh pad-to-y high 1.1 1.2 1.3 1.6 2.2 ns t inyl pad-to-y low 0.8 0.9 1.0 1.2 1.7 ns t ingh g to y high 1.4 1.6 1.8 2.1 2.9 ns t ingl g to y low 1.4 1.6 1.8 2.1 2.9 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 1.8 2.0 2.3 2.7 4.0 ns t ird2 fo=2 routing delay 2.1 2.3 2.6 3.1 4.3 ns t ird3 fo=3 routing delay 2.3 2.6 3.0 3.5 4.9 ns t ird4 fo=4 routing delay 2.6 3.0 3.3 3.9 5.4 ns t ird8 fo=8 routing delay 3.6 4.0 4.6 5.4 7.5 ns global clock network t ckh input low to high fo = 32 fo = 384 2.6 2.9 2.9 3.2 3.3 3.6 3.9 4.3 5.4 6.0 ns ns t ckl input high to low fo = 32 fo = 384 3.8 4.5 4.2 5.0 4.8 5.6 5.6 6.6 7.8 9.2 ns ns t pwh minimum pulse width high fo = 32 fo = 384 3.2 3.7 3.5 4.1 4.0 4.6 4.7 5.4 6.6 7.6 ns ns t pwl minimum pulse width low fo = 32 fo = 384 3.2 3.7 3.5 4.1 4.0 4.6 4.7 5.4 6.6 7.6 ns ns t cksw maximum skew fo = 32 fo = 384 0.3 0.3 0.4 0.4 0.4 0.4 0.5 0.5 0.7 0.7 ns ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 384 2.8 3.2 3.1 3.5 5.5 4.0 4.1 4.7 5.7 6.6 ns ns t p minimum period fo = 32 fo = 384 4.2 4.6 4.67 5.1 5.1 5.6 5.8 6.4 9.7 10.7 ns ns f max maximum frequency fo = 32 fo = 384 237 215 215 195 198 179 172 156 103 94 mhz mhz table 34 a42mx16 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-58 v6.0 ttl output module timing 5 t dlh data-to-pad high 2.5 2.8 3.2 3.7 5.2 ns t dhl data-to-pad low 3.0 3.3 3.7 4.4 6.1 ns t enzh enable pad z to high 2.7 3.0 3.4 4.0 5.6 ns t enzl enable pad z to low 3.0 3.3 3.8 4.4 6.2 ns t enhz enable pad high to z 5.4 6.0 6.8 8.0 11.2 ns t enlz enable pad low to z 5.0 5.6 6.3 7.4 10.4 ns t glh g-to-pad high 2.9 3.2 3.6 4.3 6.0 ns t ghl g-to-pad low 2.9 3.2 3.6 4.3 6.0 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 5.7 6.3 7.1 8.4 11.9 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 8.0 8.9 10.1 11.9 16.7 ns d tlh capacitive loading, low to high 0.03 0.03 0.03 0.04 0.06 ns/pf d thl capacitive loading, high to low 0.04 0.04 0.04 0.05 0.07 ns/pf cmos output module timing 5 t dlh data-to-pad high 3.2 3.6 4.0 4.7 6.6 ns t dhl data-to-pad low 2.5 2.7 3.1 3.6 5.1 ns t enzh enable pad z to high 2.7 3.0 3.4 4.0 5.6 ns t enzl enable pad z to low 3.0 3.3 3.8 4.4 6.2 ns t enhz enable pad high to z 5.4 6.0 6.8 8.0 11.2 ns t enlz enable pad low to z 5.0 5.6 6.3 7.4 10.4 ns t glh g-to-pad high 5.1 5.6 6.4 7.5 10.5 ns t ghl g-to-pad low 5.1 5.6 6.4 7.5 10.5 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 5.7 6.3 7.1 8.4 11.9 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 8.0 8.9 10.1 11.9 16.7 ns d tlh capacitive loading, low to high 0.03 0.03 0.03 0.04 0.06 ns/pf table 34 a42mx16 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-59 table 35 a42mx16 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units logic module propagation delays 1 t pd1 single module 1.9 2.1 2.4 2.8 4.0 ns t co sequential clock-to-q 2.0 2.2 2.5 3.0 4.2 ns t go latch g-to-q 1.9 2.1 2.4 2.8 4.0 ns t rs flip-flop (latch) reset-to-q 2.2 2.4 2.8 3.3 4.6 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.1 1.2 1.4 1.6 2.3 ns t rd2 fo=2 routing delay 1.5 1.6 1.8 2.1 3.0 ns t rd3 fo=3 routing delay 1.8 2.0 2.3 2.7 3.8 ns t rd4 fo=4 routing delay 2.2 2.4 2.7 3.2 4.5 ns t rd8 fo=8 routing delay 3.6 4.0 4.5 5.3 7.5 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input set-up 0.5 0.5 0.6 0.7 0.9 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 1.0 1.1 1.2 1.4 2.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.8 5.3 6.0 7.1 9.9 ns t wasyn flip-flop (latch) asynchronous pulse width 6.2 6.9 7.9 9.2 12.9 ns t a flip-flop clock input period 9.5 10.6 12.0 14.1 19.8 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.7 0.8 0.9 1.01 1.4 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.7 0.8 0.89 1.01 1.4 ns f max flip-flop (latch) clock frequency 129 117 108 94 56 mhz notes: 1. for dual-module macros use tpd1 + trd1 + taped, to + trd1 + taped, or tpd1 + trd1 + tusk, whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-60 v6.0 input module propagation delays t inyh pad-to-y high 1.5 1.6 1.9 2.2 3.1 ns t inyl pad-to-y low 1.1 1.3 1.4 1.7 2.4 ns t ingh g to y high 2.0 2.2 2.5 2.9 4.1 ns t ingl g to y low 2.0 2.2 2.5 2.9 4.1 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 2.6 2.9 3.2 3.8 5.3 ns t ird2 fo=2 routing delay 2.9 3.2 3.7 4.3 6.1 ns t ird3 fo=3 routing delay 3.3 3.6 4.1 4.9 6.8 ns t ird4 fo=4 routing delay 3.6 4.0 4.6 5.4 7.6 ns t ird8 fo=8 routing delay 5.1 5.6 6.4 7.5 10.5 ns global clock network t ckh input low to high fo = 32 fo = 384 4.4 4.8 4.8 5.3 5.5 6.0 6.5 7.1 9.0 9.9 ns ns t ckl input high to low fo = 32 fo = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns t pwh minimum pulse width high fo = 32 fo = 384 5.7 6.6 6.3 7.4 7.1 8.3 8.4 9.8 11.8 13.7 ns ns t pwl minimum pulse width low fo = 32 fo = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns t cksw maximum skew fo = 32 fo = 384 0.5 2.2 0.5 2.4 0.6 2.7 0.7 3.2 1.0 4.5 ns ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 384 3.9 4.5 4.3 4.9 4.9 5.6 5.7 6.6 8.0 9.2 ns ns t p minimum period fo = 32 fo = 384 7.0 7.7 7.8 8.6 8.4 9.3 9.7 10.7 16.2 17.8 ns ns f max maximum frequency fo = 32 fo = 384 142 129 129 117 119 108 103 94 62 56 mhz mhz table 35 a42mx16 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros use tpd1 + trd1 + taped, to + trd1 + taped, or tpd1 + trd1 + tusk, whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-61 ttl output module timing 5 t dlh data-to-pad high 3.5 3.9 4.4 5.2 7.3 ns t dhl data-to-pad low 4.1 4.6 5.2 6.1 8.6 ns t enzh enable pad z to high 3.8 4.2 4.8 5.6 7.8 ns t enzl enable pad z to low 4.2 4.6 5.3 6.2 8.7 ns t enhz enable pad high to z 7.6 8.4 9.5 11.2 15.7 ns t enlz enable pad low to z 7.0 7.8 8.8 10.4 14.5 ns t glh g-to-pad high 4.8 5.3 6.0 7.2 10.0 ns t ghl g-to-pad low 4.8 5.3 6.0 7.2 10.0 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 8.0 8.9 10.1 11.9 16.7 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 11.3 12.5 14.2 16.7 23.3 ns d tlh capacitive loading, low to high 0.04 0.04 0.05 0.06 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.05 0.06 0.07 0.10 ns/pf cmos output module timing 5 t dlh data-to-pad high 4.5 5.0 5.6 6.6 9.3 ns t dhl data-to-pad low 3.4 3.8 4.3 5.1 7.1 ns t enzh enable pad z to high 3.8 4.2 4.8 5.6 7.8 ns t enzl enable pad z to low 4.2 4.6 5.3 6.2 8.7 ns t enhz enable pad high to z 7.6 8.4 9.5 11.2 15.7 ns t enlz enable pad low to z 7.0 7.8 8.8 10.4 14.5 ns t glh g-to-pad high 7.1 7.9 8.9 10.5 14.7 ns t ghl g-to-pad low 7.1 7.9 8.9 10.5 14.7 ns t lco i/o latch clock-to-out (pad-to- pad), 64 clock loading 8.0 8.9 10.1 11.9 16.7 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 11.3 12.5 14.2 16.7 23.3 ns d tlh capacitive loading, low to high 0.04 0.04 0.05 0.06 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.05 0.06 0.07 0.10 ns/pf table 35 a42mx16 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros use tpd1 + trd1 + taped, to + trd1 + taped, or tpd1 + trd1 + tusk, whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pa d and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-62 v6.0 table 36 a42mx24 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units logic module combinatorial functions 1 t pd internal array module delay 1.2 1.3 1.5 1.8 2.5 ns t pdd internal decode module delay 1.4 1.6 1.8 2.1 3.0 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 0.8 0.9 1.0 1.2 1.7 ns t rd2 fo=2 routing delay 1.0 1.2 1.3 1.5 2.1 ns t rd3 fo=3 routing delay 1.3 1.4 1.6 1.9 2.6 ns t rd4 fo=4 routing delay 1.5 1.7 1.9 2.2 3.1 ns t rd5 fo=8 routing delay 2.4 2.7 3.0 3.6 5.0 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 1.3 1.4 1.6 1.9 2.7 ns t go latch gate-to-output 1.2 1.3 1.5 1.8 2.5 ns t sud flip-flop (latch) set-up time 0.3 0.4 0.4 0.5 0.7 ns t hd flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset-to-output 1.4 1.6 1.8 2.1 2.9 ns t suena flip-flop (latch) enable set-up 0.4 0.5 0.5 0.6 0.8 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.3 3.7 4.2 4.9 6.9 ns t wasyn flip-flop (latch) asynchronous pulse width 4.4 4.8 5.3 6.5 9.0 ns input module propagation delays t inpy input data pad-to-y 1.0 1.1 1.3 1.5 2.1 ns t ingo input latch gate-to-output 1.3 1.4 1.6 1.9 2.6 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.5 0.5 0.6 0.7 1.0 ns t ila latch active pulse width 4.7 5.2 5.9 6.9 9.7 ns notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-63 input module predicted routing delays 2 t ird1 fo=1 routing delay 1.8 2.0 2.3 2.7 3.8 ns t ird2 fo=2 routing delay 2.1 2.3 2.6 3.1 4.3 ns t ird3 fo=3 routing delay 2.3 2.5 2.9 3.4 4.8 ns t ird4 fo=4 routing delay 2.5 2.8 3.2 3.7 5.2 ns t ird8 fo=8 routing delay 3.4 3.8 4.3 5.1 7.1 ns global clock network t ckh input low to high fo=32 fo=486 2.6 2.9 2.9 3.2 3.3 3.6 3.9 4.3 5.4 5.9 ns ns t ckl input high to low fo=32 fo=486 3.7 4.3 4.1 4.7 4.6 5.4 5.4 6.3 7.6 8.8 ns ns t pwh minimum pulse width high fo=32 fo=486 2.2 2.4 2.4 2.6 2.7 3.0 3.2 3.5 4.5 4.9 ns ns t pwl minimum pulse width low fo=32 fo=486 2.2 2.4 2.4 2.6 2.7 3.0 3.2 3.5 4.5 4.9 ns ns t cksw maximum skew fo=32 fo=486 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 1.1 1.1 ns ns t suext input latch external set-up fo=32 fo=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=486 2.8 3.3 3.1 3.7 3.5 4.2 4.1 4.9 5.7 6.9 ns ns t p minimum period (1/f max ) fo=32 fo=486 4.7 5.1 5.2 5.7 5.7 6.2 6.5 7.1 10.9 11.9 ns ns table 36 a42mx24 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-64 v6.0 ttl output module timing 5 t dlh data-to-pad high 2.4 2.7 3.1 3.6 5.1 ns t dhl data-to-pad low 2.8 3.2 3.6 4.2 5.9 ns t enzh enable pad z to high 2.5 2.8 3.2 3.8 5.3 ns t enzl enable pad z to low 2.8 3.1 3.5 4.2 5.9 ns t enhz enable pad high to z 5.2 5.7 6.5 7.6 10.7 ns t enlz enable pad low to z 4.8 5.3 6.0 7.1 9.9 ns t glh g-to-pad high 2.9 3.2 3.6 4.3 6.0 ns t ghl g-to-pad low 2.9 3.2 3.6 4.3 6.0 ns t lsu i/o latch output set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 5.6 6.1 6.9 8.1 11.4 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 10.6 11.8 13.4 15.7 22.0 ns d tlh capacitive loading, low to high 0.04 0.04 0.04 0.05 0.07 ns/pf d thl capacitive loading, high to low 0.03 0.03 0.03 0.04 0.06 ns/pf table 36 a42mx24 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-65 cmos output module timing 5 t dlh data-to-pad high 3.1 3.5 3.9 4.6 6.4 ns t dhl data-to-pad low 2.4 2.6 3.0 3.5 4.9 ns t enzh enable pad z to high 2.5 2.8 3.2 3.8 5.3 ns t enzl enable pad z to low 2.8 3.1 3.5 4.2 5.8 ns t enhz enable pad high to z 5.2 5.7 6.5 7.6 10.7 ns t enlz enable pad low to z 4.8 5.3 6.0 7.1 9.9 ns t glh g-to-pad high 4.9 5.4 6.2 7.2 10.1 ns t ghl g-to-pad low 4.9 5.4 6.2 7.2 10.1 ns t lsu i/o latch set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad) 32 i/o 5.5 6.1 6.9 8.1 11.3 ns t aco array latch clock-to-out (pad- to-pad) 32 i/o 10.6 11.8 13.4 15.7 22.0 ns d tlh capacitive loading, low to high 0.04 0.04 0.04 0.05 0.07 ns/pf d thl capacitive loading, high to low 0.03 0.03 0.03 0.04 0.06 ns/pf table 36 a42mx24 timing characteristics (nom inal 5.0v operation) (continued) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-66 v6.0 table 37 a42mx24 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. logic module combinatorial functions 1 t pd internal array module delay 2.0 1.8 2.1 2.5 3.4 ns t pdd internal decode module delay 1.1 2.2 2.5 3.0 4.2 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.7 1.3 1.4 1.7 2.3 ns t rd2 fo=2 routing delay 2.0 1.6 1.8 2.1 3.0 ns t rd3 fo=3 routing delay 1.1 2.0 2.2 2.6 3.7 ns t rd4 fo=4 routing delay 1.5 2.3 2.6 3.1 4.3 ns t rd5 fo=8 routing delay 1.8 3.7 4.2 5.0 7.0 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 2.1 2.0 2.3 2.7 3.7 ns t go latch gate-to-output 3.4 1.9 2.1 2.5 3.4 ns t sud flip-flop (latch) set-up time 0.4 0.5 0.6 0.7 0.9 ns t hd flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset-to-output 2.0 2.2 2.5 2.9 4.1 ns t suena flip-flop (latch) enable set-up 0.6 0.6 0.7 0.8 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.6 5.2 5.8 6.9 9.6 ns t wasyn flip-flop (latch) asynchronous pulse width 6.1 6.8 7.7 9.0 12.6 ns input module propagation delays t inpy input data pad-to-y 1.4 1.6 1.8 2.2 3.0 ns t ingo input latch gate-to- output 1.8 1.9 2.2 2.6 3.6 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.7 0.7 0.8 1.0 1.4 ns t ila latch active pulse width 6.5 7.3 8.2 9.7 13.5 ns notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-67 input module predicted routing delays 2 t ird1 fo=1 routing delay 2.6 2.9 3.2 3.8 5.3 ns t ird2 fo=2 routing delay 2.9 3.2 3.6 4.3 6.0 ns t ird3 fo=3 routing delay 3.2 3.6 4.0 4.8 6.6 ns t ird4 fo=4 routing delay 3.5 3.9 4.4 5.2 7.3 ns t ird8 fo=8 routing delay 4.8 5.3 6.1 7.1 10.0 ns global clock network t ckh input low to high fo=32 fo=486 4.4 4.8 4.8 5.3 5.5 6.0 6.5 7.1 9.1 10.0 ns ns t ckl input high to low fo=32 fo=486 5.1 6.0 5.7 6.6 6.4 7.5 7.6 8.8 10.6 12.4 ns ns t pwh minimum pulse width high fo=32 fo=486 3.0 3.3 3.3 3.7 3.8 4.2 4.5 4.9 6.3 6.9 ns ns t pwl minimum pulse width low fo=32 fo=486 3.0 3.3 3.4 3.7 3.8 4.2 4.5 4.9 6.3 6.9 ns ns t cksw maximum skew fo=32 fo=486 0.8 0.8 0.8 0.8 1.0 1.0 1.1 1.1 1.6 1.6 ns ns t suext input latch external set-up fo=32 fo=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ttl output module timing 5 t dlh data-to-pad high 3.4 3.8 4.3 5.0 7.1 ns t dhl data-to-pad low 4.0 4.4 5.0 5.9 8.3 ns t enzh enable pad z to high 3.6 4.0 4.5 5.3 7.4 ns t enzl enable pad z to low 3.9 4.4 5.0 5.8 8.2 ns t enhz enable pad high to z 7.2 8.0 9.1 10.7 14.9 ns t enlz enable pad low to z 6.7 7.5 8.5 9.9 13.9 ns t glh g-to-pad high 4.8 5.3 6.0 7.2 10.0 ns t ghl g-to-pad low 4.8 5.3 6.0 7.2 10.0 ns t lsu i/o latch output set-up 0.7 0.7 0.8 1.0 1.4 ns table 37 a42mx24 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-68 v6.0 ttl output module timing 5 (continued) t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 7.7 8.5 9.6 11.3 15.9 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 14.8 16.5 18.7 22.0 30.8 ns d tlh capacitive loading, low to high 0.05 0.05 0.06 0.07 0.10 ns/pf d thl capacitive loading, high to low 0.04 0.04 0.05 0.06 0.08 ns/pf cmos output module timing 5 t dlh data-to-pad high 4.8 5.3 5.5 6.4 9.0 ns t dhl data-to-pad low 3.5 3.9 4.1 4.9 6.8 ns t enzh enable pad z to high 3.6 4.0 4.5 5.3 7.4 ns t enzl enable pad z to low 3.4 4.0 5.0 5.8 8.2 ns t enhz enable pad high to z 7.2 8.0 9.0 10.7 14.9 ns t enlz enable pad low to z 6.7 7.5 8.5 9.9 13.9 ns t glh g-to-pad high 6.8 7.6 8.6 10.1 14.2 ns t ghl g-to-pad low 6.8 7.6 8.6 10.1 14.2 ns t lsu i/o latch set-up 0.7 0.7 0.8 1.0 1.4 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 7.7 8.5 9.6 11.3 15.9 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 14.8 16.5 18.7 22.0 30.8 ns d tlh capacitive loading, low to high 0.05 0.05 0.06 0.07 0.10 ns/pf d thl capacitive loading, high to low 0.04 0.04 0.05 0.06 0.08 ns/pf t hext input latch external hold fo=32 fo=486 3.9 4.6 4.3 5.2 4.9 5.8 5.7 6.9 8.1 9.6 ns ns t p minimum period (1/f max ) fo=32 fo=486 7.8 8.6 8.7 9.5 9.5 10.4 10.8 11.9 18.2 19.9 ns ns table 37 a42mx24 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2?speed ??1? speed ?std? speed ??f? speed units parameter description min. max. mi n. max. min. max. min. max. min. max. notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-69 table 38 a42mx36 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units logic module combinatorial functions 1 t pd internal array module delay 1.3 1.5 1.7 2.0 2.7 ns t pdd internal decode module delay 1.6 1.8 2.0 2.4 3.3 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 0.9 1.0 1.2 1.4 2.0 ns t rd2 fo=2 routing delay 1.3 1.4 1.6 1.9 2.7 ns t rd3 fo=3 routing delay 1.6 1.8 2.0 2.4 3.4 ns t rd4 fo=4 routing delay 2.0 2.2 2.5 2.9 4.1 ns t rd5 fo=8 routing delay 3.3 3.7 4.2 4.9 6.9 ns t rdd decode-to-output routing delay 0.3 0.4 0.4 0.5 0.7 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 1.3 1.4 1.6 1.9 2.7 ns t go latch gate-to-output 1.3 1.4 1.6 1.9 2.7 ns t sud flip-flop (latch) set-up time 0.3 0.3 0.4 0.5 0.7 ns t hd flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset-to-output 1.6 1.7 2.0 2.3 3.2 ns t suena flip-flop (latch) enable set-up 0.7 0.8 0.9 1.0 1.4 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.3 3.7 4.2 4.9 6.9 ns t wasyn flip-flop (latch) asynchronous pulse width 4.4 4.8 5.5 6.4 9.0 ns synchronous sram operations t rc read cycle time 6.8 7.5 8.5 10.0 14.0 ns t wc write cycle time 6.8 7.5 8.5 10.0 14.0 ns t rckhl clock high/low time 3.4 3.8 4.3 5.0 7.0 ns t rco data valid after clock high/low 3.4 3.8 4.3 5.0 7.0 ns t adsu address/data set-up time 1.6 1.8 2.0 2.4 3.4 ns notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-70 v6.0 synchronous sram operations (continued) t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up 0.6 0.7 0.8 0.9 1.3 ns t renh read enable hold 3.4 3.8 4.3 5.0 7.0 ns t wensu write enable set-up 2.7 3.0 3.4 4.0 5.6 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 ns t bens block enable set-up 2.8 3.1 3.5 4.1 5.7 ns t benh block enable hold 0.0 0.0 0.0 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 8.1 9.0 10.2 12.0 16.8 ns t rdadv read address valid 8.8 9.8 11.1 13.0 18.2 ns t adsu address/data set-up time 1.6 1.8 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 ns t rensua read enable set-up to address valid 0.6 0.7 0.8 0.9 1.3 ns t renha read enable hold 3.4 3.8 4.3 5.0 7.0 ns t wensu write enable set-up 2.7 3.0 3.4 4.0 5.6 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.2 1.3 1.5 1.8 2.5 ns input module propagation delays t inpy input data pad-to-y 1.0 1.1 1.3 1.5 2.1 ns t ingo input latch gate-to-output 1.4 1.6 1.8 2.1 2.9 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.5 0.5 0.6 0.7 1.0 ns t ila latch active pulse width 4.7 5.2 5.9 6.9 9.7 ns table 38 a42mx36 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-71 input module predicted routing delays 2 t ird1 fo=1 routing delay 2.0 2.2 2.5 2.9 4.1 ns t ird2 fo=2 routing delay 2.3 2.6 2.9 3.4 4.8 ns t ird3 fo=3 routing delay 2.6 2.9 3.3 3.9 5.5 ns t ird4 fo=4 routing delay 3.0 3.3 3.8 4.4 6.2 ns t ird8 fo=8 routing delay 4.3 4.8 5.5 6.4 9.0 ns global clock network t ckh input low to high fo=32 fo=635 2.7 3.0 3.0 3.3 3.4 3.8 4.0 4.4 5.6 6.2 ns ns t ckl input high to low fo=32 fo=635 3.8 4.9 4.2 5.4 4.8 6.1 5.6 7.2 7.8 10.1 ns ns t pwh minimum pulse width high fo=32 fo=635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns t pwl minimum pulse width low fo=32 fo=635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns t cksw maximum skew fo=32 fo=635 0.8 0.8 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 2.8 3.3 3.2 3.7 3.6 4.2 4.2 4.9 5.9 6.9 ns ns t p minimum period (1/f max ) fo=32 fo=635 5.5 6.0 6.1 6.6 6.6 7.2 7.6 8.3 12.7 13.8 ns ns f max maximum datapath frequency fo=32 fo=635 180 166 164 151 151 139 131 121 79 73 mhz mhz ttl output module timing 5 t dlh data-to-pad high 2.6 2.8 3.2 3.8 5.3 ns t dhl data-to-pad low 3.0 3.3 3.7 4.4 6.2 ns t enzh enable pad z to high 2.7 3.0 3.3 3.9 5.5 ns t enzl enable pad z to low 3.0 3.3 3.7 4.3 6.1 ns t enhz enable pad high to z 5.3 5.8 6.6 7.8 10.9 ns table 38 a42mx36 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-72 v6.0 ttl output module timing 5 (continued) t enlz enable pad low to z 4.9 5.5 6.2 7.3 10.2 ns t glh g-to-pad high 2.9 3.3 3.7 4.4 6.1 ns t ghl g-to-pad low 2.9 3.3 3.7 4.4 6.1 ns t lsu i/o latch output set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad) 32 i/o 5.7 6.3 7.1 8.4 11.8 ns t aco array latch clock-to-out (pad- to-pad) 32 i/o 7.8 8.6 9.8 11.5 16.1 ns d tlh capacitive loading, low to high 0.07 0.08 0.09 0.10 0.14 ns/pf d thl capacitive loading, high to low 0.07 0.08 0.09 0.10 0.14 ns/pf cmos output module timing 5 t dlh data-to-pad high 3.5 3.9 4.5 5.2 7.3 ns t dhl data-to-pad low 2.5 2.7 3.1 3.6 5.1 ns t enzh enable pad z to high 2.7 3.0 3.3 3.9 5.5 ns t enzl enable pad z to low 2.9 3.3 3.7 4.3 6.1 ns t enhz enable pad high to z 5.3 5.8 6.6 7.8 10.9 ns t enlz enable pad low to z 4.9 5.5 6.2 7.3 10.2 ns t glh g-to-pad high 5.0 5.6 6.3 7.5 10.4 ns t ghl g-to-pad low 5.0 5.6 6.3 7.5 10.4 ns t lsu i/o latch set-up 0.5 0.5 0.6 0.7 1.0 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad) 32 i/o 5.7 6.3 7.1 8.4 11.8 ns t aco array latch clock-to-out (pad- to-pad) 32 i/o 7.8 8.6 9.8 11.5 16.1 ns d tlh capacitive loading, low to high 0.07 0.08 0.09 0.10 0.14 ns/pf d thl capacitive loading, high to low 0.07 0.08 0.09 0.10 0.14 ns/pf table 38 a42mx36 timing characteristic s (nominal 5.0v operation) (worst-case commercial conditions, v cca = 4.75v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-73 table 39 a42mx36 timing characteristic s (nominal 3.3v operation) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units logic module combinatorial functions 1 t pd internal array module delay 1.9 2.1 2.3 2.7 3.8 ns t pdd internal decode module delay 2.2 2.5 2.8 3.3 4.7 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 1.7 2.0 2.7 ns t rd2 fo=2 routing delay 1.8 2.0 2.3 2.7 3.7 ns t rd3 fo=3 routing delay 2.3 2.5 2.8 3.4 4.7 ns t rd4 fo=4 routing delay 2.8 3.1 3.5 4.1 5.7 ns t rd5 fo=8 routing delay 4.6 5.2 5.8 6.9 9.6 ns t rdd decode-to-output routing delay 0.5 0.5 0.6 0.7 1.0 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 1.8 2.0 2.3 2.7 3.7 ns t go latch gate-to-output 1.8 2.0 2.3 2.7 3.7 ns t sud flip-flop (latch) set-up time 0.4 0.5 0.6 0.7 0.9 ns t hd flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset-to-output 2.2 2.4 2.7 3.2 4.5 ns t suena flip-flop (latch) enable set-up 1.0 1.1 1.2 1.4 2.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.6 5.2 5.8 6.9 9.6 ns t wasyn flip-flop (latch) asynchronous pulse width 6.1 6.8 7.7 9.0 12.6 ns synchronous sram operations t rc read cycle time 9.5 10.5 11.9 14.0 19.6 ns t wc write cycle time 9.5 10.5 11.9 14.0 19.6 ns t rckhl clock high/low time 4.8 5.3 6.0 7.0 9.8 ns t rco data valid after clock high/low 4.8 5.3 6.0 7.0 9.8 ns t adsu address/data set-up time 2.3 2.5 2.8 3.4 4.8 ns notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-74 v6.0 synchronous sram operations (continued) t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up 0.9 1.0 1.1 1.3 1.8 ns t renh read enable hold 4.8 5.3 6.0 7.0 9.8 ns t wensu write enable set-up 3.8 4.2 4.8 5.6 7.8 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 ns t bens block enable set-up 3.9 4.3 4.9 5.7 8.0 ns t benh block enable hold 0.0 0.0 0.0 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 11.3 12.6 14.3 16.8 23.5 ns t rdadv read address valid 12.3 13.7 15.5 18.2 25.5 ns t adsu address/data set-up time 2.3 2.5 2.8 3.4 4.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 ns t rensua read enable set-up to address valid 0.9 1.0 1.1 1.3 1.8 ns t renha read enable hold 4.8 5.3 6.0 7.0 9.8 ns t wensu write enable set-up 3.8 4.2 4.8 5.6 7.8 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.8 2.0 2.1 2.5 3.5 ns input module propagation delays t inpy input data pad-to-y 1.4 1.6 1.8 2.1 3.0 ns t ingo input latch gate-to- output 2.0 2.2 2.5 2.9 4.1 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.7 0.7 0.8 1.0 1.4 ns t ila latch active pulse width 6.5 7.3 8.2 9.7 13.5 ns table 39 a42mx36 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-75 input module predicted routing delays 2 t ird1 fo=1 routing delay 2.8 3.1 3.5 4.1 5.7 ns t ird2 fo=2 routing delay 3.2 3.5 4.1 4.8 6.7 ns t ird3 fo=3 routing delay 3.7 4.1 4.7 5.5 7.7 ns t ird4 fo=4 routing delay 4.2 4.6 5.3 6.2 8.7 ns t ird8 fo=8 routing delay 6.1 6.8 7.7 9.0 12.6 ns global clock network t ckh input low to high fo=32 fo=635 4.6 5.0 5.1 5.6 5.7 6.3 6.7 7.4 9.3 10.3 ns ns t ckl input high to low fo=32 fo=635 5.3 6.8 5.9 7.6 6.7 8.6 7.8 10.1 11.0 14.1 ns ns t pwh minimum pulse width high fo=32 fo=635 2.5 2.8 2.7 3.1 3.1 3.5 3.6 4.1 5.1 5.7 ns ns t pwl minimum pulse width low fo=32 fo=635 2.5 2.8 2.7 3.1 3.1 3.5 3.6 4.1 5.1 5.7 ns ns t cksw maximum skew fo=32 fo=635 1.0 1.0 1.2 1.2 1.3 1.3 1.5 1.5 2.2 2.2 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 4.0 4.6 4.4 5.2 5.0 5.9 5.9 6.9 8.2 9.6 ns ns t p minimum period (1/f max ) fo=32 fo=635 9.2 9.9 10.2 11.0 11.1 12.0 12.7 13.8 21.2 23.0 ns ns f max maximum datapath frequency fo=32 fo=635 108 100 98 91 90 83 79 73 47 44 mhz mhz ttl output module timing 5 t dlh data-to-pad high 3.6 4.0 4.5 5.3 7.4 ns t dhl data-to-pad low 4.2 4.6 5.2 6.2 8.6 ns t enzh enable pad z to high 3.7 4.2 4.7 5.5 7.7 ns t enzl enable pad z to low 4.1 4.6 5.2 6.1 8.5 ns t enhz enable pad high to z 7.34 8.2 9.3 10.9 15.3 ns table 39 a42mx36 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families 1-76 v6.0 ttl output module timing 5 t enlz enable pad low to z 6.9 7.6 8.7 10.2 14.3 ns t glh g-to-pad high 4.9 5.5 6.2 7.3 10.2 ns t ghl g-to-pad low 4.9 5.5 6.2 7.3 10.2 ns t lsu i/o latch output set-up 0.7 0.7 0.8 1.0 1.4 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad) 32 i/o 7.9 8.8 10.0 11.8 16.5 ns t aco array latch clock-to-out (pad- to-pad) 32 i/o 10.9 12.1 13.7 16.1 22.5 ns d tlh capacitive loading, low to high 0.10 0.11 0.12 0.14 0.20 ns/pf d thl capacitive loading, high to low 0.10 0.11 0.12 0.14 0.20 ns/pf cmos output module timing 5 t dlh data-to-pad high 4.9 5.5 6.2 7.3 10.3 ns t dhl data-to-pad low 3.4 3.8 4.3 5.1 7.1 ns t enzh enable pad z to high 3.7 4.1 4.7 5.5 7.7 ns t enzl enable pad z to low 4.1 4.6 5.2 6.1 8.5 ns t enhz enable pad high to z 7.4 8.2 9.3 10.9 15.3 ns t enlz enable pad low to z 6.9 7.6 8.7 10.2 14.3 ns t glh g-to-pad high 7.0 7.8 8.9 10.4 14.6 ns t ghl g-to-pad low 7.0 7.8 8.9 10.4 14.6 ns t lsu i/o latch set-up 0.7 0.7 0.8 1.0 1.4 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-to-out (pad-to- pad) 32 i/o 7.9 8.8 10.0 11.8 16.5 ns table 39 a42mx36 timing characteristics (nom inal 3.3v operation) (continued) (worst-case commercial conditions, v cca = 3.0v, t j = 70c) ??3? speed ??2? speed ??1? speed ?std? speed ??f? speed parameter description min. max. min. ma x. min. max. min. max. min. max. units notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timi ng analysis or simulation is requi red to determine actual performance. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for th e input buffer latch are defined with respec t to the pad and the d input. external se tup/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
40mx and 42mx fpga families v6.0 1-77 pin descriptions clk/a/b, i/o global clock clock inputs for clock distribution networks. clk is for 40mx while clka and clkb are for 42mx devices. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk, i/o diagnostic clock clock input for diagnostic probe and device programming. dclk is acti ve when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground input low supply voltage. i/o input/output input, output, tristate or bi-d irectional buffer. input and output levels are compatib le with standard ttl and cmos specifications. unused i/os pins are configured by the designer software as shown in table 40 . in all cases, it is recommended to tie all unused mx i/o pins to low on the board. this applies to all dual- purpose pins when conf igured as i/os as well. lp low power mode controls the low power mode of all 42mx devices. the device is placed in the low power mode by connecting the lp pin to logic high. in low power mode, all i/os are tristated, all input buffers are turned off, and the core of the device is turned off. to exit the low power mode, the lp pin must be set low. the device enters the low power mode 800ns after the lp pin is driven to a logic high. it will resume normal operation in 200s after the lp pin is driven to a logic low. mode mode controls the use of multifunction pins (dclk, pra, prb, sdi, tdo). the mode pin is held high to provide verification capability. the mode pin should be terminated to gnd through a 10k ? resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. pra, i/o prb, i/o probe a/b the probe pin is used to ou tput data from any user- defined design node within the device. each diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. the probe pin can be used as a user- defined i/o when verification has been completed. the pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. the probe pin is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. qclka/b/c/d, i/o quadrant clock quadrant clock inputs for a42mx36 devices. when not used as a register control signal, these pins can function as user i/os. sdi, i/o serial data input serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdo, i/o serial data output serial data output for diagnostic probe and device programming. sdo is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdo is available for 42mx devices only. when silicon explorer ii is be ing used, sdo will act as an output while the "checksum" command is run. it will return to user i/o when "checksum" is complete. tck, i/o test clock clock signal to shift the boundary scan test (bst) data into the device. this pi n functions as an i/o when "reserve jtag" is not checked in the designer software. bst pins are only available in a42mx24 and a42mx36 devices. tdi, i/o test data in serial data input for bst instructions and data. data is shifted in on the rising edge of tck. this pin functions as an i/o when "reserve jtag " is not checked in the designer software. bst pins are only available in a42mx24 and a42mx36 devices. tdo, i/o test data out serial data output for bst in structions and test data. this pin functions as an i/o when "reserve jtag" is not checked in the designer software. bst pins are only available in a42mx24 and a42mx36 devices. table 40 configuration of unused i/os device configuration a40mx02, a40mx04 pulled low A42MX09, a42mx16 pulled low a42mx24, a42mx36 tristated
40mx and 42mx fpga families 1-78 v6.0 tms, i/o test mode select the tms pin controls the use of the ieee 1149.1 boundary scan pins (tck, tdi, tdo). in flexible mode when the tms pin is set low, the tck, tdi and tdo pins are boundary scan pins. once the boundary scan pins are in test mode, they will rema in in that mode until the internal boundary scan stat e machine reaches the "logic reset" state. at this point, the boundary sc an pins will be released and will function as regular i/o pins. the "logic reset" state is reached 5 tck cycles after the tms pin is set high. in dedicated test mode, tms functions as specified in the ieee 1149.1 specifications. ieee jtag specification recommends a 10k ? pull-up resistor on the pin. bst pins are only available in a42mx24 and a42mx36 devices. v cc supply voltage input supply voltag e for 40mx devices v cca supply voltage supply voltage for array in 42mx devices v cci supply voltage supply voltage for i/os in 42mx devices wd, i/o wide decode output when a wide decode module is used in a 42mx device this pin can be used as a dedicated output from the wide decode module. this direct connection eliminates additional interconnect dela ys associated with regular logic modules. to implement the direct i/o connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved wd pins.
40mx and 42mx fpga families v6.0 2-1 package pin assignments 44-pin plcc figure 2-1 44-pin plcc 44 1 44-pin plcc 44-pin plcc pin number a40mx02 function a40mx04 function 1i/o i/o 2i/o i/o 3v cc v cc 4i/o i/o 5i/o i/o 6i/o i/o 7i/o i/o 8i/o i/o 9i/o i/o 10 gnd gnd 11 i/o i/o 12 i/o i/o 13 i/o i/o 14 v cc v cc 15 i/o i/o 16 v cc v cc 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 gnd gnd 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 v cc v cc 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 gnd gnd 33 clk, i/o clk, i/o 34 mode mode 35 v cc v cc 36 sdi, i/o sdi, i/o 37 dclk, i/o dclk, i/o 38 pra, i/o pra, i/o 39 prb, i/o prb, i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 gnd gnd 44 i/o i/o 44-pin plcc pin number a40mx02 function a40mx04 function
40mx and 42mx fpga families 2-2 v6.0 68-pin plcc figure 2-2 68-pin plcc 1 68 68-pin plcc 44-pin plcc pin number a40mx02 function a40mx04 function 1i/oi/o 2i/oi/o 3i/oi/o 4v cc v cc 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 i/o i/o 14 gnd gnd 15 gnd gnd 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 v cc v cc 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 v cc v cc 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 gnd gnd 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 v cc v cc 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 44-pin plcc pin number a40mx02 function a40mx04 function 47 i/o i/o 48 i/o i/o 49 gnd gnd 50 i/o i/o 51 i/o i/o 52 clk, i/o clk, i/o 53 i/o i/o 54 mode mode 55 v cc v cc 56 sdi, i/o sdi, i/o 57 dclk, i/o dclk, i/o 58 pra, i/o pra, i/o 59 prb, i/o prb, i/o 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 i/o i/o 66 gnd gnd 67 i/o i/o 68 i/o i/o 44-pin plcc pin number a40mx02 function a40mx04 function
40mx and 42mx fpga families v6.0 2-3 84-pin plcc figure 2-3 84-pin plcc 184 84-pin plcc
40mx and 42mx fpga families 2-4 v6.0 84-pin plcc pin number a40mx04 function A42MX09 function a42mx16 function a42mx24 function 1i/oi/oi/oi/o 2 i/o clkb, i/o clkb, i/o clkb, i/o 3i/oi/oi/oi/o 4v cc prb, i/o prb, i/o prb, i/o 5 i/o i/o i/o wd, i/o 6 i/o gnd gnd gnd 7i/oi/oi/oi/o 8 i/o i/o i/o wd, i/o 9 i/o i/o i/o wd, i/o 10 i/o dclk, i/o dclk, i/o dclk, i/o 11 i/o i/o i/o i/o 12 nc mode mode mode 13 i/o i/o i/o i/o 14 i/o i/o i/o i/o 15 i/o i/o i/o i/o 16 i/o i/o i/o i/o 17 i/o i/o i/o i/o 18 gnd i/o i/o i/o 19 gnd i/o i/o i/o 20 i/o i/o i/o i/o 21 i/o i/o i/o i/o 22 i/o v cca v cci v cci 23 i/o v cci v cca v cca 24 i/o i/o i/o i/o 25 v cc i/o i/o i/o 26 v cc i/o i/o i/o 27 i/o i/o i/o i/o 28 i/o gnd gnd gnd 29 i/o i/o i/o i/o 30 i/o i/o i/o i/o 31 i/o i/o i/o i/o 32 i/o i/o i/o i/o 33 v cc i/o i/o i/o 34 i/o i/o i/o tms, i/o 35 i/o i/o i/o tdi, i/o 36 i/o i/o i/o wd, i/o 37 i/o i/o i/o i/o 38 i/o i/o i/o wd, i/o 39 i/o i/o i/o wd, i/o 40 gnd i/o i/o i/o 41 i/o i/o i/o i/o 42 i/o i/o i/o i/o 43 i/o v cca v cca v cca 44 i/o i/o i/o wd, i/o 45 i/o i/o i/o wd, i/o 46 v cc i/o i/o wd, i/o 47 i/o i/o i/o wd, i/o 48 i/o i/o i/o i/o 49 i/o gnd gnd gnd 50 i/o i/o i/o wd, i/o 51 i/o i/o i/o wd, i/o 52 i/o sdo, i/o sdo, i/o sdo, tdo, i/o 53 i/o i/o i/o i/o 54 i/o i/o i/o i/o 55 i/o i/o i/o i/o 56 i/o i/o i/o i/o 57 i/o i/o i/o i/o 58 i/o i/o i/o i/o 59 i/o i/o i/o i/o 60 gnd i/o i/o i/o 61 gnd i/o i/o i/o 62 i/o i/o i/o tck, i/o 63 i/o lp lp lp 64 clk, i/o v cca v cca v cca 65 i/o v cci v cci v cci 66 mode i/o i/o i/o 67 v cc i/o i/o i/o 68 v cc i/o i/o i/o 69 i/o i/o i/o i/o 70 i/o gnd gnd gnd 84-pin plcc pin number a40mx04 function A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families v6.0 2-5 71 i/o i/o i/o i/o 72 sdi, i/o i/o i/o i/o 73 dclk, i/o i/o i/o i/o 74 pra, i/o i/o i/o i/o 75 prb, i/o i/o i/o i/o 76 i/o sdi, i/o sdi, i/o sdi, i/o 77 i/o i/o i/o i/o 84-pin plcc pin number a40mx04 function A42MX09 function a42mx16 function a42mx24 function 78 i/o i/o i/o wd, i/o 79 i/o i/o i/o wd, i/o 80 i/o i/o i/o wd, i/o 81 i/o pra, i/o pra, i/o pra, i/o 82 gnd i/o i/o i/o 83 i/o clka, i/o clka, i/o clka, i/o 84 i/o v cca v cca v cca 84-pin plcc pin number a40mx04 function A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families 2-6 v6.0 100-pin pqfp package figure 2-4 100-pin pqfp package (top view) 1 100 100-pin pqfp
40mx and 42mx fpga families v6.0 2-7 100-pin pqfp pin number a40mx02 function a40mx04 function A42MX09 function a42mx16 function 1ncnci/oi/o 2 nc nc dclk, i/o dclk, i/o 3ncnci/oi/o 4 nc nc mode mode 5ncnci/oi/o 6 prb, i/o prb, i/o i/o i/o 7 i/o i/o i/o i/o 8 i/o i/o i/o i/o 9i/oi/ogndgnd 10 i/o i/o i/o i/o 11 i/o i/o i/o i/o 12 i/o i/o i/o i/o 13 gnd gnd i/o i/o 14 i/o i/o i/o i/o 15 i/o i/o i/o i/o 16 i/o i/o v cca v cca 17 i/o i/o v cci v cca 18 i/o i/o i/o i/o 19 v cc v cc i/o i/o 20 i/o i/o i/o i/o 21 i/o i/o i/o i/o 22 i/o i/o gnd gnd 23 i/o i/o i/o i/o 24 i/o i/o i/o i/o 25 i/o i/o i/o i/o 26 i/o i/o i/o i/o 27 nc nc i/o i/o 28 nc nc i/o i/o 29 nc nc i/o i/o 30 nc nc i/o i/o 31 nc i/o i/o i/o 32 nc i/o i/o i/o 33 nc i/o i/o i/o 34 i/o i/o gnd gnd 35 i/o i/o i/o i/o 36 gnd gnd i/o i/o 37 gnd gnd i/o i/o 38 i/o i/o i/o i/o 39 i/o i/o i/o i/o 40 i/o i/o v cca v cca 41 i/o i/o i/o i/o 42 i/o i/o i/o i/o 43 v cc v cc i/o i/o 44 v cc v cc i/o i/o 45 i/o i/o i/o i/o 46 i/o i/o gnd gnd 47 i/o i/o i/o i/o 48 nc i/o i/o i/o 49 nc i/o i/o i/o 50 nc i/o i/o i/o 51 nc nc i/o i/o 52 nc nc sdo, i/o sdo, i/o 53 nc nc i/o i/o 54 nc nc i/o i/o 55 nc nc i/o i/o 56 v cc v cc i/o i/o 57 i/o i/o gnd gnd 58 i/o i/o i/o i/o 59 i/o i/o i/o i/o 60 i/o i/o i/o i/o 61 i/o i/o i/o i/o 62 i/o i/o i/o i/o 63 gnd gnd i/o i/o 64 i/o i/o lp lp 65 i/o i/o v cca v cca 66 i/o i/o v cci v cci 67 i/o i/o v cca v cca 68 i/o i/o i/o i/o 69 v cc v cc i/o i/o 70 i/o i/o i/o i/o 100-pin pqfp pin number a40mx02 function a40mx04 function A42MX09 function a42mx16 function
40mx and 42mx fpga families 2-8 v6.0 71 i/o i/o i/o i/o 72 i/o i/o gnd gnd 73 i/o i/o i/o i/o 74 i/o i/o i/o i/o 75 i/o i/o i/o i/o 76 i/o i/o i/o i/o 77 nc nc i/o i/o 78 nc nc i/o i/o 79 nc nc sdi, i/o sdi, i/o 80 nc i/o i/o i/o 81 nc i/o i/o i/o 82 nc i/o i/o i/o 83 i/o i/o i/o i/o 84 i/o i/o gnd gnd 85 i/o i/o i/o i/o 100-pin pqfp pin number a40mx02 function a40mx04 function A42MX09 function a42mx16 function 86 gnd gnd i/o i/o 87 gnd gnd pra, i/o pra, i/o 88 i/o i/o i/o i/o 89 i/o i/o clka, i/o clka, i/o 90 clk, i/o clk, i/o v cca v cca 91 i/o i/o i/o i/o 92 mode mode clkb, i/o clkb, i/o 93 v cc v cc i/o i/o 94 v cc v cc prb, i/o prb, i/o 95 nc i/o i/o i/o 96 nc i/o gnd gnd 97 nc i/o i/o i/o 98 sdi, i/o sdi, i/o i/o i/o 99 dclk, i/o dclk, i/o i/o i/o 100 pra, i/o pra, i/o i/o i/o 100-pin pqfp pin number a40mx02 function a40mx04 function A42MX09 function a42mx16 function
40mx and 42mx fpga families v6.0 2-9 160-pin pqfp package figure 2-5 160-pin pqfp package (top view) 160 1 160-pin pqfp
40mx and 42mx fpga families 2-10 v6.0 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function 1 i/o i/o i/o 2 dclk, i/o dclk, i/o dclk, i/o 3nci/oi/o 4i/oi/owd, i/o 5i/oi/owd, i/o 6ncv cci v cci 7 i/o i/o i/o 8 i/o i/o i/o 9 i/o i/o i/o 10 nc i/o i/o 11 gnd gnd gnd 12 nc i/o i/o 13 i/o i/o wd, i/o 14 i/o i/o wd, i/o 15 i/o i/o i/o 16 prb, i/o prb, i/o prb, i/o 17 i/o i/o i/o 18 clkb, i/o clkb, i/o clkb, i/o 19 i/o i/o i/o 20 v cca v cca v cca 21 clka, i/o clka, i/o clka, i/o 22 i/o i/o i/o 23 pra, i/o pra, i/o pra, i/o 24 nc i/o wd, i/o 25 i/o i/o wd, i/o 26 i/o i/o i/o 27 i/o i/o i/o 28 nc i/o i/o 29 i/o i/o wd, i/o 30 gnd gnd gnd 31 nc i/o wd, i/o 32 i/o i/o i/o 33 i/o i/o i/o 34 i/o i/o i/o 35 nc v cci v cci 36 i/o i/o wd, i/o 37 i/o i/o wd, i/o 38 sdi, i/o sdi, i/o sdi, i/o 39 i/o i/o i/o 40 gnd gnd gnd 41 i/o i/o i/o 42 i/o i/o i/o 43 i/o i/o i/o 44 gnd gnd gnd 45 i/o i/o i/o 46 i/o i/o i/o 47 i/o i/o i/o 48 i/o i/o i/o 49 gnd gnd gnd 50 i/o i/o i/o 51 i/o i/o i/o 52 nc i/o i/o 53 i/o i/o i/o 54 nc v cca v cca 55 i/o i/o i/o 56 i/o i/o i/o 57 v cca v cca v cca 58 v cci v cci v cci 59 gnd gnd gnd 60 v cca v cca v cca 61 lp lp lp 62 i/o i/o tck, i/o 63 i/o i/o i/o 64 gnd gnd gnd 65 i/o i/o i/o 66 i/o i/o i/o 67 i/o i/o i/o 68 i/o i/o i/o 69 gnd gnd gnd 70 nc i/o i/o 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families v6.0 2-11 71 i/o i/o i/o 72 i/o i/o i/o 73 i/o i/o i/o 74 i/o i/o i/o 75 nc i/o i/o 76 i/o i/o i/o 77 nc i/o i/o 78 i/o i/o i/o 79 nc i/o i/o 80 gnd gnd gnd 81 i/o i/o i/o 82 sdo, i/o sdo, i/o sdo, tdo, i/o 83 i/o i/o wd, i/o 84 i/o i/o wd, i/o 85 i/o i/o i/o 86 nc v cci v cci 87 i/o i/o i/o 88 i/o i/o wd, i/o 89 gnd gnd gnd 90 nc i/o i/o 91 i/o i/o i/o 92 i/o i/o i/o 93 i/o i/o i/o 94 i/o i/o i/o 95 i/o i/o i/o 96 i/o i/o wd, i/o 97 i/o i/o i/o 98 v cca v cca v cca 99 gnd gnd gnd 100 nc i/o i/o 101 i/o i/o i/o 102 i/o i/o i/o 103 nc i/o i/o 104 i/o i/o i/o 105 i/o i/o i/o 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function 106 i/o i/o wd, i/o 107 i/o i/o wd, i/o 108 i/o i/o i/o 109 gnd gnd gnd 110 nc i/o i/o 111 i/o i/o wd, i/o 112 i/o i/o wd, i/o 113 i/o i/o i/o 114 nc v cci v cci 115 i/o i/o wd, i/o 116 nc i/o wd, i/o 117 i/o i/o i/o 118 i/o i/o tdi, i/o 119 i/o i/o tms, i/o 120 gnd gnd gnd 121 i/o i/o i/o 122 i/o i/o i/o 123 i/o i/o i/o 124 nc i/o i/o 125 gnd gnd gnd 126 i/o i/o i/o 127 i/o i/o i/o 128 i/o i/o i/o 129 nc i/o i/o 130 gnd gnd gnd 131 i/o i/o i/o 132 i/o i/o i/o 133 i/o i/o i/o 134 i/o i/o i/o 135 nc v cca v cca 136 i/o i/o i/o 137 i/o i/o i/o 138 nc v cca v cca 139 v cci v cci v cci 140 gnd gnd gnd 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families 2-12 v6.0 141 nc i/o i/o 142 i/o i/o i/o 143 i/o i/o i/o 144 i/o i/o i/o 145 gnd gnd gnd 146 nc i/o i/o 147 i/o i/o i/o 148 i/o i/o i/o 149 i/o i/o i/o 150 nc v cca v cca 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function 151 nc i/o i/o 152 nc i/o i/o 153 nc i/o i/o 154 nc i/o i/o 155 gnd gnd gnd 156 i/o i/o i/o 157 i/o i/o i/o 158 i/o i/o i/o 159 mode mode mode 160 gnd gnd gnd 160-pin pqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families v6.0 2-13 208-pin pqfp package figure 2-6 208-pin pqfp package (top view) 208-pin pqfp 1 208
40mx and 42mx fpga families 2-14 v6.0 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 1 gnd gnd gnd 2ncv cca v cca 3 mode mode mode 4 i/o i/o i/o 5 i/o i/o i/o 6 i/o i/o i/o 7 i/o i/o i/o 8 i/o i/o i/o 9nci/oi/o 10 nc i/o i/o 11 nc i/o i/o 12 i/o i/o i/o 13 i/o i/o i/o 14 i/o i/o i/o 15 i/o i/o i/o 16 nc i/o i/o 17 v cca v cca v cca 18 i/o i/o i/o 19 i/o i/o i/o 20 i/o i/o i/o 21 i/o i/o i/o 22 gnd gnd gnd 23 i/o i/o i/o 24 i/o i/o i/o 25 i/o i/o i/o 26 i/o i/o i/o 27 gnd gnd gnd 28 v cci v cci v cci 29 v cca v cca v cca 30 i/o i/o i/o 31 i/o i/o i/o 32 v cca v cca v cca 33 i/o i/o i/o 34 i/o i/o i/o 35 i/o i/o i/o 36 i/o i/o i/o 37 i/o i/o i/o 38 i/o i/o i/o 39 i/o i/o i/o 40 i/o i/o i/o 41 nc i/o i/o 42 nc i/o i/o 43 nc i/o i/o 44 i/o i/o i/o 45 i/o i/o i/o 46 i/o i/o i/o 47 i/o i/o i/o 48 i/o i/o i/o 49 i/o i/o i/o 50 nc i/o i/o 51 nc i/o i/o 52 gnd gnd gnd 53 gnd gnd gnd 54 i/o tms, i/o tms, i/o 55 i/o tdi, i/o tdi, i/o 56 i/o i/o i/o 57 i/o wd, i/o wd, i/o 58 i/o wd, i/o wd, i/o 59 i/o i/o i/o 60 v cci v cci v cci 61 nc i/o i/o 62 nc i/o i/o 63 i/o i/o i/o 64 i/o i/o i/o 65 i/o i/o qclka, i/o 66 i/o wd, i/o wd, i/o 67 nc wd, i/o wd, i/o 68 nc i/o i/o 69 i/o i/o i/o 70 i/o wd, i/o wd, i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
40mx and 42mx fpga families v6.0 2-15 71 i/o wd, i/o wd, i/o 72 i/o i/o i/o 73 i/o i/o i/o 74 i/o i/o i/o 75 i/o i/o i/o 76 i/o i/o i/o 77 i/o i/o i/o 78 gnd gnd gnd 79 v cca v cca v cca 80 nc v cci v cci 81 i/o i/o i/o 82 i/o i/o i/o 83 i/o i/o i/o 84 i/o i/o i/o 85 i/o wd, i/o wd, i/o 86 i/o wd, i/o wd, i/o 87 i/o i/o i/o 88 i/o i/o i/o 89 nc i/o i/o 90 nc i/o i/o 91 i/o i/o qclkb, i/o 92 i/o i/o i/o 93 i/o wd, i/o wd, i/o 94 i/o wd, i/o wd, i/o 95 nc i/o i/o 96 nc i/o i/o 97 nc i/o i/o 98 v cci v cci v cci 99 i/o i/o i/o 100 i/o wd, i/o wd, i/o 101 i/o wd, i/o wd, i/o 102 i/o i/o i/o 103 sdo, i/o sdo, tdo, i/o sdo, tdo, i/o 104 i/o i/o i/o 105 gnd gnd gnd 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 106 nc v cca v cca 107 i/o i/o i/o 108 i/o i/o i/o 109 i/o i/o i/o 110 i/o i/o i/o 111 i/o i/o i/o 112 nc i/o i/o 113 nc i/o i/o 114 nc i/o i/o 115 nc i/o i/o 116 i/o i/o i/o 117 i/o i/o i/o 118 i/o i/o i/o 119 i/o i/o i/o 120 i/o i/o i/o 121 i/o i/o i/o 122 i/o i/o i/o 123 i/o i/o i/o 124 i/o i/o i/o 125 i/o i/o i/o 126 gnd gnd gnd 127 i/o i/o i/o 128 i/o tck, i/o tck, i/o 129lplplp 130 v cca v cca v cca 131 gnd gnd gnd 132 v cci v cci v cci 133 v cca v cca v cca 134 i/o i/o i/o 135 i/o i/o i/o 136 v cca v cca v cca 137 i/o i/o i/o 138 i/o i/o i/o 139 i/o i/o i/o 140 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
40mx and 42mx fpga families 2-16 v6.0 141 nc i/o i/o 142 i/o i/o i/o 143 i/o i/o i/o 144 i/o i/o i/o 145 i/o i/o i/o 146 nc i/o i/o 147 nc i/o i/o 148 nc i/o i/o 149 nc i/o i/o 150 gnd gnd gnd 151 i/o i/o i/o 152 i/o i/o i/o 153 i/o i/o i/o 154 i/o i/o i/o 155 i/o i/o i/o 156 i/o i/o i/o 157 gnd gnd gnd 158 i/o i/o i/o 159 sdi, i/o sdi, i/o sdi, i/o 160 i/o i/o i/o 161 i/o wd, i/o wd, i/o 162 i/o wd, i/o wd, i/o 163 i/o i/o i/o 164 v cci v cci v cci 165 nc i/o i/o 166 nc i/o i/o 167 i/o i/o i/o 168 i/o wd, i/o wd, i/o 169 i/o wd, i/o wd, i/o 170 i/o i/o i/o 171 nc i/o qclkd, i/o 172 i/o i/o i/o 173 i/o i/o i/o 174 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 175 i/o i/o i/o 176 i/o wd, i/o wd, i/o 177 i/o wd, i/o wd, i/o 178 pra, i/o pra, i/o pra, i/o 179 i/o i/o i/o 180 clka, i/o clka, i/o clka, i/o 181 nc i/o i/o 182 nc v cci v cci 183 v cca v cca v cca 184 gnd gnd gnd 185 i/o i/o i/o 186 clkb, i/o clkb, i/o clkb, i/o 187 i/o i/o i/o 188 prb, i/o prb, i/o prb, i/o 189 i/o i/o i/o 190 i/o wd, i/o wd, i/o 191 i/o wd, i/o wd, i/o 192 i/o i/o i/o 193 nc i/o i/o 194 nc wd, i/o wd, i/o 195 nc wd, i/o wd, i/o 196 i/o i/o qclkc, i/o 197 nc i/o i/o 198 i/o i/o i/o 199 i/o i/o i/o 200 i/o i/o i/o 201 nc i/o i/o 202 v cci v cci v cci 203 i/o wd, i/o wd, i/o 204 i/o wd, i/o wd, i/o 205 i/o i/o i/o 206 i/o i/o i/o 207 dclk, i/o dclk, i/o dclk, i/o 208 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
40mx and 42mx fpga families v6.0 2-17 240-pin pqfp package figure 2-7 240-pin pqfp package (top view) 240-pin pqfp 1 240
40mx and 42mx fpga families 2-18 v6.0 240-pin pqfp pin number a42mx36 function 1i/o 2 dclk, i/o 3i/o 4i/o 5i/o 6wd, i/o 7wd, i/o 8v cci 9i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 qclkc, i/o 16 i/o 17 wd, i/o 18 wd, i/o 19 i/o 20 i/o 21 wd, i/o 22 wd, i/o 23 i/o 24 prb, i/o 25 i/o 26 clkb, i/o 27 i/o 28 gnd 29 v cca 30 v cci 31 i/o 32 clka, i/o 33 i/o 34 pra, i/o 35 i/o 36 i/o 37 wd, i/o 38 wd, i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 qclkd, i/o 46 i/o 47 wd, i/o 48 wd, i/o 49 i/o 50 i/o 51 i/o 52 v cci 53 i/o 54 wd, i/o 55 wd, i/o 56 i/o 57 sdi, i/o 58 i/o 59 v cca 60 gnd 61 gnd 62 i/o 63 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 240-pin pqfp pin number a42mx36 function 71 v cci 72 i/o 73 i/o 74 i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 v cca 86 i/o 87 i/o 88 v cca 89 v cci 90 v cca 91 lp 92 tck, i/o 93 i/o 94 gnd 95 i/o 96 i/o 97 i/o 98 i/o 99 i/o 100 i/o 101 i/o 102 i/o 103 i/o 104 i/o 105 i/o 240-pin pqfp pin number a42mx36 function 106 i/o 107 i/o 108 v cci 109 i/o 110 i/o 111 i/o 112 i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 v cca 119 gnd 120 gnd 121 gnd 122 i/o 123 sdo, tdo, i/o 124 i/o 125 wd, i/o 126 wd, i/o 127 i/o 128 v cci 129 i/o 130 i/o 131 i/o 132 wd, i/o 133 wd, i/o 134 i/o 135 qclkb, i/o 136 i/o 137 i/o 138 i/o 139 i/o 140 i/o 240-pin pqfp pin number a42mx36 function
40mx and 42mx fpga families v6.0 2-19 141 i/o 142 wd, i/o 143 wd, i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 i/o 149 i/o 150 v cci 151 v cca 152 gnd 153 i/o 154 i/o 155 i/o 156 i/o 157 i/o 158 i/o 159 wd, i/o 160 wd, i/o 161 i/o 162 i/o 163 wd, i/o 164 wd, i/o 165 i/o 166 qclka, i/o 167 i/o 168 i/o 169 i/o 170 i/o 171 i/o 172 v cci 173 i/o 174 wd, i/o 175 wd, i/o 240-pin pqfp pin number a42mx36 function 176 i/o 177 i/o 178 tdi, i/o 179 tms, i/o 180 gnd 181 v cca 182 gnd 183 i/o 184 i/o 185 i/o 186 i/o 187 i/o 188 i/o 189 i/o 190 i/o 191 i/o 192 v cci 193 i/o 194 i/o 195 i/o 196 i/o 197 i/o 198 i/o 199 i/o 200 i/o 201 i/o 202 i/o 203 i/o 204 i/o 205 i/o 206 v cca 207 i/o 208 i/o 209 v cca 210 v cci 240-pin pqfp pin number a42mx36 function 211 i/o 212 i/o 213 i/o 214 i/o 215 i/o 216 i/o 217 i/o 218 i/o 219 v cca 220 i/o 221 i/o 222 i/o 223 i/o 224 i/o 225 i/o 226 i/o 227 v cci 228 i/o 229 i/o 230 i/o 231 i/o 232 i/o 233 i/o 234 i/o 235 i/o 236 i/o 237 gnd 238 mode 239 v cca 240 gnd 240-pin pqfp pin number a42mx36 function
40mx and 42mx fpga families 2-20 v6.0 80-pin vqfp figure 2-8 80-pin vqfp 80 1 80-pin vqfp
40mx and 42mx fpga families v6.0 2-21 80-pin vqfp pin number a40mx02 function a40mx04 function 1i/oi/o 2nci/o 3nci/o 4nci/o 5i/oi/o 6i/oi/o 7gndgnd 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 v cc v cc 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 nc i/o 18 nc i/o 19 nc i/o 20 v cc v cc 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 gnd gnd 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 v cc v cc 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 nc i/o 42 nc i/o 43 nc i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 gnd gnd 48 i/o i/o 49 i/o i/o 50 clk, i/o clk, i/o 51 i/o i/o 52 mode mode 53 v cc v cc 54 nc i/o 80-pin vqfp pin number a40mx02 function a40mx04 function 55 nc i/o 56 nc i/o 57 sdi, i/o sdi, i/o 58 dclk, i/o dclk, i/o 59 pra, i/o pra, i/o 60 nc nc 61 prb, i/o prb, i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 gnd gnd 69 i/o i/o 70 i/o i/o 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 v cc v cc 75 i/o i/o 76 i/o i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 80-pin vqfp pin number a40mx02 function a40mx04 function
40mx and 42mx fpga families 2-22 v6.0 100-pin vqfp package figure 2-9 100-pin vqfp package (top view) 1 100-pin vqfp 100
40mx and 42mx fpga families v6.0 2-23 100-pin vqfp package pin number A42MX09 function a42mx16 function 1i/oi/o 2 mode mode 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7gndgnd 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 i/o i/o 14 v cca nc 15 v cci v cci 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 gnd gnd 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 gnd gnd 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 v cca v cca 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 gnd gnd 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 sdo, i/o sdo, i/o 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 gnd gnd 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 i/o i/o 60 i/o i/o 61 i/o i/o 62 lp lp 63 v cca v cca 64 v cci v cci 65 v cca v cca 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 gnd gnd 100-pin vqfp package pin number A42MX09 function a42mx16 function 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 i/o i/o 76 i/o i/o 77 sdi, i/o sdi, i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 gnd gnd 83 i/o i/o 84 i/o i/o 85 pra, i/o pra, i/o 86 i/o i/o 87 clka, i/o clka, i/o 88 v cca v cca 89 i/o i/o 90 clkb, i/o clkb, i/o 91 i/o i/o 92 prb, i/o prb, i/o 93 i/o i/o 94 gnd gnd 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 i/o i/o 99 i/o i/o 100 dclk, i/o dclk, i/o 100-pin vqfp package pin number A42MX09 function a42mx16 function
40mx and 42mx fpga families 2-24 v6.0 176-pin tqfp package figure 2-10 176-pin tqfp pac kage (top view) 176-pin tqfp 176 1
40mx and 42mx fpga families v6.0 2-25 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function 1 gnd gnd gnd 2 mode mode mode 3 i/o i/o i/o 4 i/o i/o i/o 5 i/o i/o i/o 6 i/o i/o i/o 7 i/o i/o i/o 8ncnci/o 9 i/o i/o i/o 10 nc i/o i/o 11 nc i/o i/o 12 i/o i/o i/o 13 nc v cca v cca 14 i/o i/o i/o 15 i/o i/o i/o 16 i/o i/o i/o 17 i/o i/o i/o 18 gnd gnd gnd 19 nc i/o i/o 20 nc i/o i/o 21 i/o i/o i/o 22 nc i/o i/o 23 gnd gnd gnd 24 nc v cci v cci 25 v cca v cca v cca 26 nc i/o i/o 27 nc i/o i/o 28 v cci v cca v cca 29 nc i/o i/o 30 i/o i/o i/o 31 i/o i/o i/o 32 i/o i/o i/o 33 nc nc i/o 34 i/o i/o i/o 35 i/o i/o i/o 36 i/o i/o i/o 37 nc i/o i/o 38 nc nc i/o 39 i/o i/o i/o 40 i/o i/o i/o 41 i/o i/o i/o 42 i/o i/o i/o 43 i/o i/o i/o 44 i/o i/o i/o 45 gnd gnd gnd 46 i/o i/o tms, i/o 47 i/o i/o tdi, i/o 48 i/o i/o i/o 49 i/o i/o wd, i/o 50 i/o i/o wd, i/o 51 i/o i/o i/o 52 nc v cci v cci 53 i/o i/o i/o 54 nc i/o i/o 55 nc i/o wd, i/o 56 i/o i/o wd, i/o 57 nc nc i/o 58 i/o i/o i/o 59 i/o i/o wd, i/o 60 i/o i/o wd, i/o 61 nc i/o i/o 62 i/o i/o i/o 63 i/o i/o i/o 64 nc i/o i/o 65 i/o i/o i/o 66 nc i/o i/o 67 gnd gnd gnd 68 v cca v cca v cca 69 i/o i/o wd, i/o 70 i/o i/o wd, i/o 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families 2-26 v6.0 71 i/o i/o i/o 72 i/o i/o i/o 73 i/o i/o i/o 74 nc i/o i/o 75 i/o i/o i/o 76 i/o i/o i/o 77 nc nc wd, i/o 78 nc i/o wd, i/o 79 i/o i/o i/o 80 nc i/o i/o 81 i/o i/o i/o 82 nc v cci v cci 83 i/o i/o i/o 84 i/o i/o wd, i/o 85 i/o i/o wd, i/o 86 nc i/o i/o 87 sdo, i/o sdo, i/o sdo, tdo, i/o 88 i/o i/o i/o 89 gnd gnd gnd 90 i/o i/o i/o 91 i/o i/o i/o 92 i/o i/o i/o 93 i/o i/o i/o 94 i/o i/o i/o 95 i/o i/o i/o 96 nc i/o i/o 97 nc i/o i/o 98 i/o i/o i/o 99 i/o i/o i/o 100 i/o i/o i/o 101 nc nc i/o 102 i/o i/o i/o 103 nc i/o i/o 104 i/o i/o i/o 105 i/o i/o i/o 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function 106 gnd gnd gnd 107 nc i/o i/o 108 nc i/o tck, i/o 109lplplp 110 v cca v cca v cca 111 gnd gnd gnd 112 v cci v cci v cci 113 v cca v cca v cca 114 nc i/o i/o 115 nc i/o i/o 116 nc v cca v cca 117 i/o i/o i/o 118 i/o i/o i/o 119 i/o i/o i/o 120 i/o i/o i/o 121 nc nc i/o 122 i/o i/o i/o 123 i/o i/o i/o 124 nc i/o i/o 125 nc i/o i/o 126 nc nc i/o 127 i/o i/o i/o 128 i/o i/o i/o 129 i/o i/o i/o 130 i/o i/o i/o 131 i/o i/o i/o 132 i/o i/o i/o 133 gnd gnd gnd 134 i/o i/o i/o 135 sdi, i/o sdi, i/o sdi, i/o 136 nc i/o i/o 137 i/o i/o wd, i/o 138 i/o i/o wd, i/o 139 i/o i/o i/o 140 nc v cci v cci 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families v6.0 2-27 141 i/o i/o i/o 142 i/o i/o i/o 143 nc i/o i/o 144 nc i/o wd, i/o 145 nc nc wd, i/o 146 i/o i/o i/o 147 nc i/o i/o 148 i/o i/o i/o 149 i/o i/o i/o 150 i/o i/o wd, i/o 151 nc i/o wd, i/o 152 pra, i/o pra, i/o pra, i/o 153 i/o i/o i/o 154 clka, i/o clka, i/o clka, i/o 155 v cca v cca v cca 156 gnd gnd gnd 157 i/o i/o i/o 158 clkb, i/o clkb, i/o clkb, i/o 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function 159 i/o i/o i/o 160 prb, i/o prb, i/o prb, i/o 161 nc i/o wd, i/o 162 i/o i/o wd, i/o 163 i/o i/o i/o 164 i/o i/o i/o 165 nc nc wd, i/o 166 nc i/o wd, i/o 167 i/o i/o i/o 168 nc i/o i/o 169 i/o i/o i/o 170 nc v cci v cci 171 i/o i/o wd, i/o 172 i/o i/o wd, i/o 173 nc i/o i/o 174 i/o i/o i/o 175 dclk, i/o dclk, i/o dclk, i/o 176 i/o i/o i/o 176-pin tqfp pin number A42MX09 function a42mx16 function a42mx24 function
40mx and 42mx fpga families 2-28 v6.0 208-pin cqfp ) figure 2-11 208-pin cqfp (top view) a42mx36 208-pin cqfp pin #1 index 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104 10 5 10 6 10 7 10 8 10 9 11 0 111 11 2 11 3 14 9 15 0 151 15 2 15 3 15 4 15 5 15 6 52 51 50 49 48 47 46 45 44 8 7 6 5 4 3 2 1
40mx and 42mx fpga families v6.0 2-29 208-pin cqfp pin number a42mx36 function 1gnd 2v cca 3mode 4i/o 5i/o 6i/o 7i/o 8i/o 9i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 v cca 18 i/o 19 i/o 20 i/o 21 i/o 22 gnd 23 i/o 24 i/o 25 i/o 26 i/o 27 gnd 28 v cci 29 v cca 30 i/o 31 i/o 32 v cca 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 gnd 53 gnd 54 tms, i/o 55 tdi, i/o 56 i/o 57 wd, i/o 58 wd, i/o 59 i/o 60 v cci 61 i/o 62 i/o 63 i/o 64 i/o 65 qclka, i/o 66 wd, i/o 67 wd, i/o 68 i/o 69 i/o 70 wd, i/o 208-pin cqfp pin number a42mx36 function 71 wd, i/o 72 i/o 73 i/o 74 i/o 75 i/o 76 i/o 77 i/o 78 gnd 79 v cca 80 v cci 81 i/o 82 i/o 83 i/o 84 i/o 85 wd, i/o 86 wd, i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 qclkb, i/o 92 i/o 93 wd, i/o 94 wd, i/o 95 i/o 96 i/o 97 i/o 98 v cci 99 i/o 100 wd, i/o 101 wd, i/o 102 i/o 103 tdo, i/o 104 i/o 105 gnd 208-pin cqfp pin number a42mx36 function 106 v cca 107 i/o 108 i/o 109 i/o 110 i/o 111 i/o 112 i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 i/o 122 i/o 123 i/o 124 i/o 125 i/o 126 gnd 127 i/o 128 tck, i/o 129 lp 130 v cca 131 gnd 132 v cci 133 v cca 134 i/o 135 i/o 136 v cca 137 i/o 138 i/o 139 i/o 140 i/o 208-pin cqfp pin number a42mx36 function
40mx and 42mx fpga families 2-30 v6.0 141 i/o 142 i/o 143 i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 i/o 149 i/o 150 gnd 151 i/o 152 i/o 153 i/o 154 i/o 155 i/o 156 i/o 157 gnd 208-pin cqfp pin number a42mx36 function 158 i/o 159 sdi, i/o 160 i/o 161 wd, i/o 162 wd, i/o 163 i/o 164 v cci 165 i/o 166 i/o 167 i/o 168 wd, i/o 169 wd, i/o 170 i/o 171 qclkd, i/o 172 i/o 173 i/o 174 i/o 208-pin cqfp pin number a42mx36 function 175 i/o 176 wd, i/o 177 wd, i/o 178 pra, i/o 179 i/o 180 clka, i/o 181 i/o 182 v cci 183 v cca 184 gnd 185 i/o 186 clkb, i/o 187 i/o 188 prb, i/o 189 i/o 190 wd, i/o 191 wd, i/o 208-pin cqfp pin number a42mx36 function 192 i/o 193 i/o 194 wd, i/o 195 wd, i/o 196 qclkc, i/o 197 i/o 198 i/o 199 i/o 200 i/o 201 i/o 202 v cci 203 wd, i/o 204 wd, i/o 205 i/o 206 i/o 207 dclk, i/o 208 i/o 208-pin cqfp pin number a42mx36 function
40mx and 42mx fpga families v6.0 2-31 256-pin cqfp figure 2-12 256-pin cqfp (top view) a42mx36 256-pin cqfp pin #1 index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 13 0 131 132 133 13 4 135 13 6 137 18 5 18 6 18 7 18 8 18 9 19 0 191 19 2 64 63 62 61 60 59 58 57 56 8 7 6 5 4 3 2 1
40mx and 42mx fpga families 2-32 v6.0 256-pin cqfp pin number a42mx36 function 1nc 2gnd 3i/o 4i/o 5i/o 6i/o 7i/o 8i/o 9i/o 10 gnd 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 v cca 27 i/o 28 i/o 29 v cca 30 v cci 31 gnd 32 v cca 33 lp 34 tck, i/o 35 i/o 36 gnd 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 gnd 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 v cca 61 gnd 62 gnd 63 nc 64 nc 65 nc 66 i/o 67 sdo, tdo, i/o 68 i/o 69 wd, i/o 70 wd, i/o 256-pin cqfp pin number a42mx36 function 71 i/o 72 v cci 73 i/o 74 i/o 75 i/o 76 wd, i/o 77 gnd 78 wd, i/o 79 i/o 80 qclkb, i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 wd, i/o 88 wd, i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 v cci 96 v cca 97 gnd 98 gnd 99 i/o 100 i/o 101 i/o 102 i/o 103 i/o 104 i/o 105 wd, i/o 256-pin cqfp pin number a42mx36 function 106 wd, i/o 107 i/o 108 i/o 109 wd, i/o 110 wd, i/o 111 i/o 112 qclka, i/o 113 i/o 114 gnd 115 i/o 116 i/o 117 i/o 118 i/o 119 v cci 120 i/o 121 wd, i/o 122 wd, i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 gnd 128 nc 129 nc 130 nc 131 gnd 132 i/o 133 i/o 134 i/o 135 i/o 136 i/o 137 i/o 138 i/o 139 gnd 140 i/o 256-pin cqfp pin number a42mx36 function
40mx and 42mx fpga families v6.0 2-33 141 i/o 142 i/o 143 i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 i/o 149 i/o 150 i/o 151 i/o 152 i/o 153 i/o 154 i/o 155 v cca 156 i/o 157 i/o 158 v cca 159 v cci 160 gnd 161 i/o 162 i/o 163 i/o 164 i/o 165 gnd 166 i/o 167 i/o 168 i/o 169 i/o 170 v cca 171 i/o 172 i/o 173 i/o 174 i/o 175 i/o 256-pin cqfp pin number a42mx36 function 176 i/o 177 i/o 178 i/o 179 i/o 180 gnd 181 i/o 182 i/o 183 i/o 184 i/o 185 i/o 186 i/o 187 i/o 188 mode 189 v cca 190 gnd 191 nc 192 nc 193 nc 194 i/o 195 dclk, i/o 196 i/o 197 i/o 198 i/o 199 wd, i/o 200 wd, i/o 201 v cci 202 i/o 203 i/o 204 i/o 205 i/o 206 gnd 207 i/o 208 i/o 209 qclkc, i/o 210 i/o 256-pin cqfp pin number a42mx36 function 211 wd, i/o 212 wd, i/o 213 i/o 214 i/o 215 wd, i/o 216 wd, i/o 217 i/o 218 prb, i/o 219 i/o 220 clkb, i/o 221 i/o 222 gnd 223 gnd 224 v cca 225 v cci 226 i/o 227 clka, i/o 228 i/o 229 pra, i/o 230 i/o 231 i/o 232 wd, i/o 233 wd, i/o 234 i/o 235 i/o 236 i/o 237 i/o 238 i/o 239 i/o 240 qclkd, i/o 241 i/o 242 wd, i/o 243 gnd 244 wd, i/o 245 i/o 256-pin cqfp pin number a42mx36 function 246 i/o 247 i/o 248 v cci 249 i/o 250 wd, i/o 251 wd, i/o 252 i/o 253 sdi, i/o 254 i/o 255 gnd 256 nc 256-pin cqfp pin number a42mx36 function
40mx and 42mx fpga families 2-34 v6.0 272-pin bga package figure 2-13 272-pin bga package (top view) 272-pin pbga 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y
40mx and 42mx fpga families v6.0 2-35 272-pin pbga pin number a42mx36 function a1 gnd a2 gnd a3 i/o a4 wd, i/o a5 i/o a6 i/o a7 wd, i/o a8 wd, i/o a9 i/o a10 i/o a11 clka a12 i/o a13 i/o a14 i/o a15 i/o a16 wd, i/o a17 i/o a18 i/o a19 gnd a20 gnd b1 gnd b2 gnd b3 dclk, i/o b4 i/o b5 i/o b6 i/o b7 wd, i/o b8 i/o b9 prb, i/o b10 i/o b11 i/o b12 wd, i/o b13 i/o b14 i/o b15 wd, i/o b16 i/o b17 wd, i/o b18 i/o b19 gnd b20 gnd c1 i/o c2 mode c3 gnd c4 i/o c5 wd, i/o c6 i/o c7 qclkc, i/o c8 i/o c9 i/o c10 clkb c11 pra, i/o c12 wd, i/o c13 i/o c14 qclkd, i/o c15 i/o c16 wd, i/o c17 sdi, i/o c18 i/o c19 i/o c20 i/o d1 i/o d2 i/o d3 i/o d4 i/o d5 v cci d6 i/o d7 i/o d8 v cca d9 wd, i/o d10 v cci 272-pin pbga pin number a42mx36 function d11 i/o d12 v cci d13 i/o d14 v cci d15 i/o d16 v cca d17 gnd d18 i/o d19 i/o d20 i/o e1 i/o e2 i/o e3 i/o e4 v cca e17 v cci e18 i/o e19 i/o e20 i/o f1 i/o f2 i/o f3 i/o f4 v cci f17 i/o f18 i/o f19 i/o f20 i/o g1 i/o g2 i/o g3 i/o g4 v cci g17 v cci g18 i/o g19 i/o g20 i/o h1 i/o 272-pin pbga pin number a42mx36 function h2 i/o h3 i/o h4 v cca h17 i/o h18 i/o h19 i/o h20 i/o j1 i/o j2 i/o j3 i/o j4 v cci j9 gnd j10 gnd j11 gnd j12 gnd j17 v cca j18 i/o j19 i/o j20 i/o k1 i/o k2 i/o k3 i/o k4 v cci k9 gnd k10 gnd k11 gnd k12 gnd k17 i/o k18 v cca k19 v cca k20 lp l1 i/o l2 i/o l3 v cca l4 v cca 272-pin pbga pin number a42mx36 function
40mx and 42mx fpga families 2-36 v6.0 l9 gnd l10 gnd l11 gnd l12 gnd l17 v cci l18 i/o l19 i/o l20 tck, i/o m1 i/o m2 i/o m3 i/o m4 v cci m9 gnd m10 gnd m11 gnd m12 gnd m17 i/o m18 i/o m19 i/o m20 i/o n1 i/o n2 i/o n3 i/o n4 v cci n17 v cci n18 i/o n19 i/o n20 i/o p1 i/o p2 i/o p3 i/o p4 v cca p17 i/o p18 i/o p19 i/o 272-pin pbga pin number a42mx36 function p20 i/o r1 i/o r2 i/o r3 i/o r4 v cci r17 v cci r18 i/o r19 i/o r20 i/o t1 i/o t2 i/o t3 i/o t4 i/o t17 v cca t18 i/o t19 i/o t20 i/o u1 i/o u2 i/o u3 i/o u4 i/o u5 v cci u6 wd, i/o u7 i/o u8 i/o u9 wd, i/o u10 v cca u11 v cci u12 i/o u13 i/o u14 qclkb, i/o u15 i/o u16 v cci u17 i/o u18 gnd 272-pin pbga pin number a42mx36 function u19 i/o u20 i/o v1 i/o v2 i/o v3 gnd v4 gnd v5 i/o v6 i/o v7 i/o v8 wd, i/o v9 i/o v10 i/o v11 i/o v12 i/o v13 wd, i/o v14 i/o v15 wd, i/o v16 i/o v17 i/o v18 sdo, tdo, i/o v19 i/o v20 i/o w1 gnd w2 gnd w3 i/o w4 tms, i/o w5 i/o w6 i/o w7 i/o w8 wd, i/o w9 wd, i/o w10 i/o w11 i/o w12 i/o 272-pin pbga pin number a42mx36 function w13 wd, i/o w14 i/o w15 i/o w16 wd, i/o w17 i/o w18 wd, i/o w19 gnd w20 gnd y1 gnd y2 gnd y3 i/o y4 tdi, i/o y5 wd, i/o y6 i/o y7 qclka, i/o y8 i/o y9 i/o y10 i/o y11 i/o y12 i/o y13 i/o y14 i/o y15 i/o y16 i/o y17 i/o y18 wd, i/o y19 gnd y20 gnd 272-pin pbga pin number a42mx36 function
fpga families 40mx and 42mx v6.0 3-1 datasheet information list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v 6. 0 ) page v5.1 the "ease of integration" section was updated. 1-i the "temperature grade offerings" section is new. 1-iii the "speed grade offerings" section is new. 1-iii the "general description" section was updated. 1-1 the "multiplex i/o modules" section was updated. 1-6 the "user security" section was updated. 1-6 table 1 voltage support of mx devices was updated. 1-7 the "power dissipation" section was updated. 1-8 the "static power component" section was updated. 1-8 the "equivalent capacitance" section was updated. 1-8 figure 1-13 silicon explorer ii setup with 42mx was updated. 1-10 table 4 supported bst public instructions was updated. 1-11 figure 1-14 42mx ieee 1149.1 boundary scan circuitry was updated. 1-11 table 5 boundary scan pin configuration and functionality was updated. 1-12 the "development tool support" section was updated. 1-13 the table 7 absolute maximum ratings for 42mx devices* and the ta b l e 6 a b s o l u t e maximum ratings for 40mx devices* were updated. 1-14 the table 9 5v ttl elec trical specifications was updated. 1-15 the table 13 3.3v lvttl electrical specifications was updated. 1-17 in the "mixed 5.0v/3.3v electrical specif ications" section , table 14 absolute maximum ratings* , table 15 recommended operating conditions , and table 16 mixed 5.0v/3.3v electrical specifications were updated. 1-18 the table 17 dc specification (5.0v pci signaling) 1 was updated. 1-19 the table 19 dc specification (3.3v pci signaling) 1 was updated. 1-20 the junction temperature (t j ) section, "package thermal characteristics" section , and the tables were updated. 1-22 figure 1-17 40mx timing model* was updated. 1-23 figure 1-19 42mx timing model (logic functions using quadrant clocks) 1-24 the figure 1-20 42mx timing model (sram functions) was updated. 1-24 the figure 1-27 output buffer latches was updated. 1-27 the table 22 42mx temperature and voltage derating factors is new. 1-31 the table 23 40mx temperature and voltage derating factors is new. 1-32 the "pin descriptions" section was updated. 1-77 in the 100-pin pqfp table, the following pins changed: pin 64 (42mx09 and 42mx16) has changed to lp 2-7
fpga families 40mx and 42mx 3-2 v6.0 datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. 5.1 in the 160-pin pqfp table, the following pins changed: pin 61 (42mx09, 42mx16, an d 42mx64) has changed to lp 2-10 in the 208-pin pqfp table, the following pins changed: pin 129 (42mx09, 42mx16, and 42mx64) has changed to lp pin 198 (42mx09) has changed to i/o 2-14 the n the 240-pin pqfp table, the following pins changed: pin 91 (42mx36) has changed to lp 2-18 in the 100-pin vqfp package table, the following pins changed: pin 62 (42mx09 and 42mx16) has changed to lp 2-23 in the 176-pin tqfp table, the following pins changed: pin 109 (42mx09 and 42mx16) has changed to lp 2-25 in the 272-pin pbga table, the following pins changed: pin k20 (42mx36) has changed to lp 2-35 v5.0 the "low power mode" section was updated. 1-7 footnote 8 in the table 9 5v ttl elec trical specifications was updated. 1-15 footnote 8 in the table 13 3.3v lvttl electrical specifications was updated. 1-17 v4.0.1 because the changes in this data sheet are exte nsive and technical in nature, this should be viewed as a new document. please read it as you would a data sheet that is published for the first time. all note that the ?package characteristics and mech anical drawings? section has been eliminated from the data sheet. the mechanical drawings are now contained in a separate document, ?package characteristics and mechanical draw ings,? available on the actel web site. previous version changes in current version (v 6. 0 ) page
5172136-8/01.04 http://www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0)1276.401450 fax +44 (0)1276.401490 actel japan exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong 39th floor, on e pacific place 88 queensway, admiralty hong kong phone +852.227.35712 fax +852.227.35999

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